Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

Memory Standards Supported by Intel® Arria® 10 Devices

The I/Os are designed to provide high performance support for existing and emerging external memory standards.
Table 20.  Memory Standards Supported by the Hard Memory ControllerThis table lists the overall capability of the hard memory controller. For specific details, refer to the External Memory Interface Spec Estimator and Intel® Arria® 10 Device Datasheet.
Memory Standard Rate Support Ping Pong PHY Support

Maximum Frequency

(MHz)

DDR4 SDRAM

Quarter rate Yes 1,067
— 1,200

DDR3 SDRAM

Half rate Yes 533
— 667
Quarter rate Yes 1,067
— 1,067

DDR3L SDRAM

Half rate Yes 533
— 667
Quarter rate Yes 933
— 933
LPDDR3 SDRAM Half rate — 533
Quarter rate — 800
Table 21.  Memory Standards Supported by the Soft Memory Controller
Memory Standard Rate Support

Maximum Frequency

(MHz)

RLDRAM 3 11

Quarter rate 1,200

QDR IV SRAM11

Quarter rate 1,067

QDR II SRAM

Full rate 333
Half rate 633
QDR II+ SRAM Full rate 333
Half rate 633
QDR II+ Xtreme SRAM Full rate 333
Half rate 633
Table 22.  Memory Standards Supported by the HPS Hard Memory ControllerThe hard processor system (HPS) is available in Intel® Arria® 10 SoC devices only.
Memory Standard Rate Support

Maximum Frequency

(MHz)

DDR4 SDRAM

Half rate 1,200

DDR3 SDRAM

Half rate 1,067

DDR3L SDRAM

Half rate 933
Related Information
11 Intel® Arria® 10 devices support this external memory interface using hard PHY with soft memory controller.
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