Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

10 Gbps Ethernet Support

The Intel® Arria® 10 enhanced PCS hard IP supports 10GBASE-R PCS compliant with IEEE 802.3 10 Gbps Ethernet (10GbE). The integrated hard IP support for 10GbE and the 10 Gbps transceivers save external PHY cost, board space, and system power.

The scalable hard IP supports multiple independent 10GbE ports while using a single PLL for all the 10GBASE-R PCS instantiations, which saves on core logic resources and clock networks:

  • Simplifies multiport 10GbE systems compared to XAUI interfaces that require an external XAUI-to-10G PHY.
  • Incorporates Electronic Dispersion Compensation (EDC), which enables direct connection to standard 10 Gbps XFP and SFP+ pluggable optical modules.
  • Supports backplane Ethernet applications and includes a hard 10GBASE-KR Forward Error Correction (FEC) circuit that you can use for 10 Gbps and 40 Gbps applications.

The 10 Gbps Ethernet PCS hard IP and 10GBASE-KR FEC are present in every transceiver channel.

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