Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

PCS Protocol Support

This table lists some of the protocols supported by the Intel® Arria® 10 transceiver PCS. For more information about the blocks in the transmitter and receiver data paths, refer to the related information.

Protocol Data Rate (Gbps) Transceiver IP PCS Support
PCIe Gen3 x1, x2, x4, x8 8.0 Native PHY (PIPE) Standard PCS and PCIe Gen3 PCS
PCIe Gen2 x1, x2, x4, x8 5.0 Native PHY (PIPE) Standard PCS
PCIe Gen1 x1, x2, x4, x8 2.5 Native PHY (PIPE) Standard PCS
1000BASE-X Gigabit Ethernet 1.25 Native PHY Standard PCS
1000BASE-X Gigabit Ethernet with IEEE 1588v2 1.25 Native PHY Standard PCS
10GBASE-R 10.3125 Native PHY Enhanced PCS
10GBASE-R with IEEE 1588v2 10.3125 Native PHY Enhanced PCS
10GBASE-R with KR FEC 10.3125 Native PHY Enhanced PCS
10GBASE-KR and 1000BASE-X 10.3125 1G/10GbE and 10GBASE-KR PHY Standard PCS and Enhanced PCS
Interlaken (CEI-6G/11G) 3.125 to 17.4 Native PHY Enhanced PCS
SFI-S/SFI-5.2 11.2 Native PHY Enhanced PCS
10G SDI 10.692 Native PHY Enhanced PCS
CPRI 6.0 (64B/66B) 0.6144 to 10.1376 Native PHY Enhanced PCS
CPRI 4.2 (8B/10B) 0.6144 to 9.8304 Native PHY Standard PCS
OBSAI RP3 v4.2 0.6144 to 6.144 Native PHY Standard PCS
SD-SDI/HD-SDI/3G-SDI 0.14312 to 2.97 Native PHY Standard PCS
Related Information
12 The 0.143 Gbps data rate is supported using oversampling of user logic that you must implement in the FPGA fabric.
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