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Key Advantages of Intel® Arria® 10 Devices
Summary of Intel® Arria® 10 Features
Intel® Arria® 10 Device Variants and Packages
I/O Vertical Migration for Intel® Arria® 10 Devices
Adaptive Logic Module
Variable-Precision DSP Block
Embedded Memory Blocks
Clock Networks and PLL Clock Sources
FPGA General Purpose I/O
External Memory Interface
PCIe Gen1, Gen2, and Gen3 Hard IP
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Low Power Serial Transceivers
SoC with Hard Processor System
Dynamic and Partial Reconfiguration
Enhanced Configuration and Configuration via Protocol
SEU Error Detection and Correction
Power Management
Incremental Compilation
Document Revision History for Intel® Arria® 10 Device Overview
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FPGA Configuration and HPS Booting
The FPGA fabric and HPS in the SoC FPGA must be powered at the same time. You can reduce the clock frequencies or gate the clocks to reduce dynamic power.
Once powered, the FPGA fabric and HPS can be configured independently thus providing you with more design flexibility:
- You can boot the HPS independently. After the HPS is running, the HPS can fully or partially reconfigure the FPGA fabric at any time under software control. The HPS can also configure other FPGAs on the board through the FPGA configuration controller.
- Configure the FPGA fabric first, and then boot the HPS from memory accessible to the FPGA fabric.