Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Public
Document Table of Contents

2. About the Serial Lite III Streaming Intel® FPGA IP

The Serial Lite III Streaming Intel® FPGA IP is a high-speed serial communication protocol for chip-to-chip, board-to-board, and backplane application data transfers. This protocol offers high bandwidth, low overhead frames, low I/O count, and supports scalability in both number of lanes and lane speed.

The Serial Lite III Streaming Intel® FPGA IP incorporates a media access control (MAC) block, a physical coding sublayer (PCS), and a physical media attachment (PMA). The IP transmits and receives streaming data through the Avalon® streaming interface on its FPGA fabric interface.

Figure 1. Typical Application Using Simplex Core
Figure 2. Typical System Application Using Duplex Core