Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Arria® 10 and Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Stratix® 10 Devices 3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Arria® 10 and Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Stratix® 10 Devices 5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

Document Version Quartus® Prime Version IP Version Changes
2024.05.23 24.1 20.1.0 Updated to Nios II to Nios® V
2024.01.16 23.3 20.0.2
  • Updated Table: Serial Lite III Streaming Intel® FPGA IP to add final support to the Cyclone® 10 GX Device Family Support category.
2023.10.02 23.3 20.0.2
  • Updated Table: Serial Lite III Streaming Intel® FPGA IP .
2023.05.26 22.4 20.0.0
  • Updated Reset section.
2022.12.19 22.4 20.0.0
  • Added support for Cyclone® 10 GX devices.
  • Added Release Information and IP Information for Cyclone® 10 GX devices.
  • Updated note in Figure Serial Lite III Streaming IP core with Source and Sink Cores and Serial Lite III Streaming IP core Duplex Core.
  • Added Resource Utilization table for Cyclone® 10 GX devices.
2021.11.01 21.3 19.3.0
  • Added support for QuestaSim* simulator.
  • Removed references to NCSim simulator throughout the document.
  • Updated the device family support for Table: Serial Lite III Streaming Intel® FPGA IP .
2021.08.09 18.1.1 18.1.1
  • Updated the description for the ready signal in the following tables:
    • Table: Serial Lite III Streaming Source Core Signals for Stratix® 10 L-tile and H-tile Devices
    • Table: Serial Lite III Streaming Sink Core Signals for Stratix® 10 L-tile and H-tile Devices
  • Updated the description for the ready_tx and ready_rx signals in Table: Serial Lite III Streaming Duplex Core Signals for Stratix® 10 L-tile, H-tile, and E-tile Devices.
2021.04.23 18.1.1 18.1.1
  • Renamed the document title to Serial Lite III Streaming Intel® FPGA IP User Guide.
  • Updated Table: Serial Lite III Streaming Duplex Core Signals for Stratix® 10 L-tile, H-tile, and E-tile Devices:
    • Updated clock domain and description for interface_clock_reset_rx.
    • Added information for interface_clock_reset_tx.
  • Made editorial edits throughout the document.
2020.07.10 18.1.1 18.1.1
  • Rephrased Transceiver Native PHY Arria® 10/ Cyclone® 10 GX FPGA Intel IP core to Transceiver Native PHY IP for Arria® 10 devices.
2020.05.05 18.1.1 18.1.1
  • Added Serial Lite III Streaming IP latency values for standard and advanced modes in 28 Gbps transceiver rate.
  • Rebranded the following:
    • Avalon-MM interface to Avalon memory-mapped interface
    • Avalon-ST interface to Avalon streaming interface
2019.02.25 18.1.1 18.1.1 Added Stratix® 10 E-Tile Transceiver PHY User Guide: PMA Adaptation link in the Parameter Settings for Stratix® 10 Devices topic, to provide more information on parameters in the PMA Adaptation tab.
2019.01.17 18.1 18.1 Updated phy_mgmt_addr signal description for Stratix® 10 device in L-Tile/H-Tile/E-Tile Transceiver Native PHY Stratix® 10 IP Core Signals (Interlaken Mode) table.
2018.09.24 18.1 18.1
  • Updated resource utilization with E-tile transceiver support.
  • Added Serial Lite III Streaming Intel FPGA IP Transceiver Tiles Support in Intel Stratix 10 Devices table.
  • Added note to clarify parameters that are not supported in E-tile transceiver.
  • Added the following registers in Source Configuration and Status Registers for MAC and Sink Configuration and Status Registers for MAC tables:
    • TX MAC Status
    • RX MAC Status
  • Removed the following bits in Sink Configuration and Status Registers for MAC table:
    • RX Loss of Frame Lock Consolidated Status bit 2 of RX Error Status Register
    • RX Loss of Frame Lock Interrupt bit 2 of RX Error Interrupt Enable Register
  • Added the following bits in Sink Configuration and Status Registers for MAC table:
    • RX Data Error bit 11 of RX Error Status Register
    • RX Adaptation FIFO Overflow bit 7 of RX Error Status Register
    • RX Data Error Enable bit 11 of RX Error Interrupt Enable Register
    • RX Adaptation FIFO Overflow Enable bit 7 of RX Error Interrupt Enable Register
  • Added a note to clarify that Riviera Pro is not supported for E-tile transceiver.
  • Updated Error Detection, Reporting, and Recovering Mechanism topic with reporting and recovering mechanisms.
  • Updated core latency for Stratix® 10 E-tile transceiver devices in Latency Measurement for Duplex Core table.
  • Added Stratix® 10 E-tile transceiver devices standard and advanced clocking mode block diagrams.
  • Updated reset scheme for Stratix® 10 E-tile transceiver devices.
  • Added IP core link up sequences with waveforms in Link-Up Sequence topic.
2018.05.07 18.0 18.0
  • Updated 28 Gbps with 4 data lanes support for Stratix® 10 devices.
  • Updated resources for 28 Gbps with 4 data lanes in SerialLite III Streaming IP Core Performance and Resource Utilization table.
  • Reorganized SerialLite III Streaming IP Core Functional Description and SerialLite III Streaming IP Core Clocking Guidelines chapters.
  • Added SerialLite III Streaming Intel FPGA IP Core Design Examples section.
Date Version Changes
December 2017 2017.12.27
  • Updated transceiver data rate from 25 Gbps to 17.4 Gbps for GXT selection in Transceiver Channel Typeparameter.
November 2017 2017.11.06
  • Updated parameter settings for Stratix® 10, Arria® 10, and Stratix V and Arria V GZ devices.
  • Updated transfer data rate supported in Stratix® 10 devices.
  • Added performance, transceiver speed grade and resource utilization for 25 and 28 Gbps data rate for Stratix® 10 devices.
  • Added a note to specify no support for simplex receiver mode in Stratix® 10 devices for data rate greater than 17.4 Gbps.
May 2017 2017.05.08
  • Clarified the device family support for Stratix® 10 devices.
  • Clarified the exact replica of output data support for pure streaming operation in the following locations:
    • Continuous Mode sub-topic
    • IP Core Architecture topic
    • Comparing Standard and Advanced Clocking Modes table
    • Standard Clocking Mode sub-topic
    • Sink Adaptation Module sub-topic
    • Standard Clocking Mode vs Advanced Clocking Mode topic
  • Removed the Continuous vs. Burst Mode Characteristics table.
  • Updated the SerialLite III Streaming IP Core FPGA Performance and Resource Utilization table for Arria® 10, Stratix® V GX and Arria® V GZ, and Stratix® 10 devices.
  • Updated the SerialLite III Streaming IP Core Parameters table:
    • Removed the Streaming Mode parameter.
    • Updated the description for User input parameter.
  • Updated the description in the Specifying IP Core Parameters and Options topic.
  • Updated the Simulation Parameters sub-topic to include testbench default simulation parameters for Arria® 10 and Stratix® 10 devices.
  • Updated the Simulator column in the Intel FPGA IP Core Simulation Scripts table.
  • Updated the Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode topic.
  • Updated the description of the phy_mgmt_clk signal in the SerialLite III Streaming IP Core Clock Domains and Signals table.
  • Updated the SerialLite III Streaming Sink Core topic.
  • Updated the Latency Measurement for Duplex Core table in the Core Latency topic to include Stratix® 10 device.
  • Updated the second note in the Reset topic.
  • Updated the description in the CRC-32 Error Injection topic.
  • Updated the Clocking Structure for Stratix 10 Devices topic:
    • Added the Source and Sink descriptions for interface_clock signal in the Stratix® 10 Clocks in Standard Clocking Mode table.
    • Added tx_clkout and rx_clkout signals in the Stratix® 10 Clocks in Advanced Clocking Mode table.
    • Updated the description for Choosing TX PLL Type for Stratix® 10 Devices sub-topic.
  • Updated the Clocking Structure For Arria® 10 Devices topic:
    • Updated the Clocking Structure for Arria® 10 Devices figure.
    • Updated the Source and Sink descriptions for interface_clock signal in the Arria® 10 Clocks in Standard Clocking Mode table.
    • Updated the description for Choosing TX PLL Type for Arria® 10 Devices sub-topic.
  • Updated the Serial Lite III Streaming Link Debugging topic:
    • Updated the Source Core Link Debugging Flow Chart figure.
    • Updated the Source Link Debugging Signals table to include Stratix® 10 support.
    • Updated the Sink Core Link Debugging Flow Chart figure.
    • Updated the Sink Link Debugging Signals table to include Stratix® 10 support.
  • Updated the Error Handling topic:
    • Updated the sink core error flag.
    • Added information on error status on error_rx signal condition.
  • Updated the Register Map for SerialLite III Streaming MAC table:
    • Added RX Error Status register.
    • Updated the source register name for 0x0090 from TX Error to TX Error Status.
    • Removed RX MAC status.
  • Updated the Configuration and Status Registers topic.
  • Minor typographical corrections and stylistic changes.
October 2016 2016.10.28
  • Added information about Stratix® 10 support.
  • Update document template.
May 2016 2016.05.02
November 2015 2015.11.02
  • Updated the IP Core Performance and Resource Utilization table.
  • Added a new topic—Intel FPGA IP Evaluation Mode Timeout Behavior
  • Added a link to Introduction to Altera IP Cores.
  • Added a note in "Altera IP Core Simulation Scripts" to recommend that you run the msim_setup.tcl script in the ModelSim-Altera Simulator Tcl console.
  • Changed the minimum required gap between bursts to one user clock cycle.
  • Added information about using I/O PLL to generate the core clock and user clock signals for Arria 10 devices.
  • Added a new parameter—Burst Gap.
  • Updated the parameter description for Interface clock frequency, Core clock frequency, and fPLL reference clock frequency.
  • Updated the parameter value for Core clock frequency.
  • Updated the PMA width for Interlaken mode to 64 bits for Arria 10 devices.
  • Updated all SerialLite III Streaming IP Core block diagrams.
  • Removed the Source PPM Absorption module from the core.
  • Changed the bit function and description for error (source core) and error_tx (duplex core) signals.
  • Updated the description of link_up_rx signal.
  • Added "Interlaken PHY Register Descriptions" table to specify the registers to access using the Avalon-MM PHY management interface.
  • Updated the design example to support Arria 10 devices.
  • Changed the target development kit to Transceiver Signal Integrity Development Kit, Stratix V GX Edition.
  • Updated the design operation names in the Design Example Operation topic.
  • Changed the sink link debug signal from rx_crc32 to rx_crc32err.
  • Updated the sink core conditions in the Error Handling topic.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.04
  • Updated the IP Core Performance and Resource Utilization table.
  • Changed the width of sync_rx and sync_tx signals from 4 to 8 bits in Signals.
  • Added external serial loopback in Testbench and Testbench.
December 2014 2014.12.15 Described Arria 10 support for up to 17.4 Gbps transceiver data rate. Updated core latency numbers. Updated the Transmission Overheads and Lane Rate Calculations. Minor text changes.
August 2014 2014.08.18 Added information about Arria 10 support.
June 2014 2014.06.30

Replaced references to MegaWizard Plug-In Manager with IP catalog or parameter editor. Minor text changes.

November 2013 2013.11.04
  • Added information on CRC-32 error injection.
  • Added information on the FIFO ECC protection option.
May 2013 2013.05.13

Initial release

Level Two Title