Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Public
Document Table of Contents

5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode

For Arria® 10, Cyclone® 10 GX, and Stratix® 10 with L-tile and H-tile devices, this block is an instance of the Native PHY IP core configured for Interlaken - TX only operation. The PMA width for Interlaken mode is 64 bits.

For Stratix V and Arria V GZ devices, the Interlaken PHY IP TX core is an instance of the Interlaken PHY IP core configured for TX only operation. The PMA width for Interlaken mode is 40 bits. The core requires a Transceiver Reconfiguration Controller for transceiver calibration. The number of channels programmed for configuration in the Transceiver Reconfiguration Controller depends on the IP core's operation mode. For example, if the design is a source core only design or a duplex core design, the reconfiguration interfaces is equal to the number of lanes x 2.