Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Arria® 10 and Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Stratix® 10 Devices 3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Arria® 10 and Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Stratix® 10 Devices 5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices)

In this mode, you must specify the user clock frequency through the Serial Lite III Streaming Intel FPGA IP core parameter editor. Based on the user clock frequency value, the Quartus® Prime software automatically calculates the lane rate and core clock.

The parameter editor provides guidance in selecting a source user clock frequency that meets the transceiver data rate constraints. For more information about the lane rate calculation, refer to the “Transmission Overheads and Lane Rate Calculations” section.

The core operates at higher clock rates in Advanced Clocking Mode. Therefore, when operating in this mode, it may be difficult to close timing at higher data rates (for example, 12 to 15 G) or higher number of lanes. You can implement the following qsf assignment when seeing timing recovery violations from sink coreclkin reset synchronizer to the sink transfer paths: 
set_instance_assignment -name GLOBAL_SIGNAL OFF -to 
*seriallite_iii_streaming*clock_gen:sink_clock_gen|dp_sync:coreclkin_reset_sync|dp_sync_regstage:dp_sync_stage_2*o*

The Serial Lite III Streaming Intel FPGA IP core uses the transmit serial clock bus (tx_serial_clk) and the tx_pll_locked signal to connect the external transmit PLL to the L-Tile/H-Tile Transceiver Native PHY Stratix® 10 FPGA IP core.

Note: For sink core, the IP core does not provide any adaptation module and does not support any PPM tolerance between the interface_clock and user interface clock. Users should consider a design that can manage the PPM differences between interface_clock and user interface clock.

Figure below shows the source and sink variant clocking structure for advanced clocking mode in Stratix® 10 devices.

Figure 20. Advanced Clocking Mode Structure for Stratix® 10 L-tile/H-tile Transceiver Devices
Figure 21. Advanced Clocking Mode Structure for Stratix® 10 E-tile Transceiver Devices
Table 38.   Stratix® 10 Clocks in Advanced Clocking Mode
Clock Name Description
Source
user_clock User-defined. This clock is determined by the required throughput of the user application. For example, if the user interface is 384-bits wide (6 lanes × 64 bit/lane) and the required throughput is 120 Gbps, the user_clock frequency is 312.5 MHz. This clock is an input to the IP core and you should toggle this at the specified frequency.
tx_serial_clk This clock should toggle at one-half the data rate of the transceiver lane. When you enter the user_clock frequency in the IP parameter editor, the per lane data rate is calculated. Use that value and divided it by two to determine the tx_serial_clk. You are required to instantiate the TX PLL. In the Serial Lite III Streaming design example, an example of the TX PLL (ATX PLL) is generated with the IP core and is configured with the required reference clock and tx_serial_clk.
Note: This signal is not available when you select E-Tile as as the transceiver tile.
tx_clkout This clock is not exposed to the user. The frequency of tx_clkout is the data rate divided by 64.
interface_clock This is an internal clock and it is not exposed to the user. The frequency of this clock is derived from the transceiver data rate. The frequency is lane data rate divided by 64.
Sink
xcvr_pll_ref_clk This reference clock is used by the CDR unit in the transceiver. It serves as a reference for the CDR to be able to recover the clock from the serial line. The frequency of this clock must match the frequency you select in the IP parameter editor. It should also match the frequency of the tx_pll_ref_clk reference clock for the TX PLL at the Sink variant for Stratix® 10 L-tile/H-tile transceiver devices.
rx_clkout This clock is not exposed to the user. The frequency of rx_clkout is the data rate divided by 64.
interface_clock This clock is derived from the transceiver data. It is lane data rate divided by 64. It is an output of the IP core and should be used to clock the RX user application.
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