Serial Lite III Streaming Intel® FPGA IP User Guide

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ID 683330
Date 5/23/2024
Public
Document Table of Contents
Document Table of Contents x
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference 2. About the Serial Lite III Streaming Intel® FPGA IP 3. Getting Started 4. Serial Lite III Streaming IP Core Design Examples 5. Serial Lite III Streaming Intel® FPGA IP Functional Description 6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines 7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers 8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines 9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives 10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide
2. About the Serial Lite III Streaming Intel® FPGA IP x
2.1. Serial Lite III Streaming Intel® FPGA IP Protocol 2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes 2.3. Performance and Resource Utilization
2.2. Serial Lite III Streaming Intel® FPGA IP Protocol Operating Modes x
2.2.1. Continuous Mode 2.2.2. Burst Mode
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Intel® FPGA IP Evaluation Mode 3.3. Specifying IP Core Parameters and Options 3.4. Serial Lite III Streaming Intel® FPGA IP Parameters 3.5. Transceiver Reconfiguration Controller for Stratix® V and Arria® V GZ Designs 3.6. IP Generation Output ( Quartus® Prime Pro Edition) 3.7. IP Core Generation Output ( Quartus® Prime Standard Edition) 3.8. Simulating
3.2. Intel® FPGA IP Evaluation Mode x
3.2.1. Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying IP Core Parameters and Options x
3.3.1. Serial Lite III Streaming Intel® FPGA IP Parameter Editor 3.3.2. Arria® 10 and Cyclone® 10 GX Designs
3.4. Serial Lite III Streaming Intel® FPGA IP Parameters x
3.4.1. Parameters 3.4.2. Parameter Settings for Stratix® 10 Devices 3.4.3. Parameter Settings for Arria® 10 and Cyclone® 10 GX Devices 3.4.4. Parameter Settings for Stratix V and Arria V GZ Devices
3.8. Simulating x
3.8.1. Simulating Intel® FPGA IP Cores 3.8.2. Simulation Parameters 3.8.3. Simulating and Verifying the Design
4. Serial Lite III Streaming IP Core Design Examples x
4.1. Serial Lite III Streaming IP Core Design Example for Stratix® 10 Devices 4.2. Serial Lite III Streaming IP Core Design Example for Arria® 10 and Cyclone® 10 GX Devices 4.3. Serial Lite III Streaming IP Design Examples for Stratix® V Devices
5. Serial Lite III Streaming Intel® FPGA IP Functional Description x
5.1. IP Architecture 5.2. Transmission Overheads and Lane Rate Calculations 5.3. Reset 5.4. Link-Up Sequence 5.5. Error Detection, Reporting, and Recovering Mechanism 5.6. CRC-32 Error Injection 5.7. FIFO ECC Protection 5.8. User Data Interface Waveforms 5.9. Signals 5.10. Accessing Configuration and Status Registers
5.1. IP Architecture x
5.1.1. Serial Lite III Streaming Source Core 5.1.2. Serial Lite III Streaming Sink Core 5.1.3. Serial Lite III Streaming IP Core Duplex Core 5.1.4. Interlaken PHY IP Duplex Core or Native PHY IP Duplex Core - Interlaken Mode or PCS Gearbox Mode 5.1.5. Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V GZ Variations
5.1.1. Serial Lite III Streaming Source Core x
5.1.1.1. Source Application Module 5.1.1.2. Source Adaptation Module 5.1.1.3. Interlaken PHY IP TX Core or Native PHY IP TX Core - Interlaken Mode 5.1.1.4. Source Clock Generator
5.1.2. Serial Lite III Streaming Sink Core x
5.1.2.1. Sink Application Module 5.1.2.2. Sink Adaptation Module 5.1.2.3. Lane Alignment Module 5.1.2.4. Interlaken PHY IP RX Core or Native PHY IP RX Core - Interlaken Mode 5.1.2.5. Sink Clock Generator
5.9. Signals x
5.9.1. Serial Lite III Streaming Intel® FPGA IP Interface Signals 5.9.2. Signals for Stratix® 10 Devices 5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices 5.9.4. Signals for Stratix® V and Arria® V GZ Devices
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines x
6.1. Standard Clocking Mode 6.2. Advanced Clocking Mode 6.3. Standard Clocking Mode vs Advanced Clocking Mode 6.4. Clocking Implementation Guidelines 6.5. Core Latency
6.1. Standard Clocking Mode x
6.1.1. Standard Clocking Mode in Serial Lite III Streaming Intel® FPGA IP Core ( Stratix® 10 Devices) 6.1.2. Standard Clocking Mode in Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.2. Advanced Clocking Mode x
6.2.1. Advanced Clocking Mode Structure for Serial Lite III Streaming Intel FPGA IP Core ( Stratix® 10 Devices) 6.2.2. Advanced Clocking Mode Structure For Arria® 10, Cyclone® 10 GX, Stratix® V, and Arria® V Devices
6.4. Clocking Implementation Guidelines x
6.4.1. Choosing TX PLL Type
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers x
7.1. Register Map 7.2. Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines x
8.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging
8.2. Serial Lite III Streaming Intel® FPGA IP Link Debugging x
8.2.1. Source Core Link Debugging 8.2.2. Sink Core Link Debugging
1. Serial Lite III Streaming Intel® FPGA IP Quick Reference
2. About the Serial Lite III Streaming Intel® FPGA IP
3. Getting Started
4. Serial Lite III Streaming IP Core Design Examples
5. Serial Lite III Streaming Intel® FPGA IP Functional Description
6. Serial Lite III Streaming Intel® FPGA IP Clocking Guidelines
7. Serial Lite III Streaming Intel® FPGA IP Configuration and Status Registers
8. Serial Lite III Streaming Intel® FPGA IP Debugging Guidelines
9. Serial Lite III Streaming Intel® FPGA IP User Guide Archives
10. Document Revision History for the Serial Lite III Streaming Intel® FPGA IP User Guide

3.3. Specifying IP Core Parameters and Options

Follow these steps to specify IP core parameters and options.
  1. In the Platform Designer IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The parameter editor appears.
  2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target FPGA device family and output file HDL preference. Click OK.
  3. Specify parameters and options for your IP variation:
    • Optionally select preset parameter values. Presets specify all initial parameter values for specific applications (where provided).
    • Specify parameters defining the IP core functionality, port configurations, and device-specific features.
    • Specify options for generation of a timing netlist, simulation model, testbench, or example design (where applicable).
    • Specify options for processing the IP core files in other EDA tools.
  4. Click Finish to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .qsys IP variation file and HDL files for synthesis and simulation. Some IP cores also simultaneously generate a testbench or example design for hardware testing.

The top-level IP variation is added to the current Quartus® Prime project. Click Project > Add/Remove Files in Project to manually add a .qsys ( Quartus® Prime Standard Edition) or .ip ( Quartus® Prime Pro Edition) file to a project. Make appropriate pin assignments to connect ports.


Section Content
Serial Lite III Streaming Intel FPGA IP Parameter Editor
Arria 10 and Cyclone 10 GX Designs

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