Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 5/23/2024
Public
Document Table of Contents

5.9.3. Signals for Arria® 10 and Cyclone® 10 GX Devices

Note: For Arria® 10 and Cyclone® 10 GX devices, the phy_mgmt bus interface connects to the reconfiguration interface of the instantiated Native PHY IP core.
Table 28.   Serial Lite III Streaming Arria® 10 and Cyclone® 10 GX IP Core Source Core Signals

Signal

Width

Clock Domain

Direction

Description

tx_serial_clk N N/A

Input

This signal is a high-speed serial clock input from the external transceiver PLL. The width is the same as the number of lanes specified in the parameter editor. Each bit of the vector corresponds to serial clock of the transmit channel.

N represents the number of lanes.

tx_pll_locked 1 N/A Input This signal indicates that all external transceiver PLLs are locked. If more than one external transceiver PLL is required for higher lanes, each instantiation outputs a bit that indicates whether the PLL providing the high-speed clock for a corresponding transceiver has achieved its lock status. The pll_locked output signal from the external transceiver PLLs should be ANDed together before being input to the IP core.
core_reset

1

N/A

Input

Asynchronous master reset for the core. Assert this signal high to reset the MAC layer, except for the fPLL that is available in standard clocking mode.

Intel recommends that you tie this signal to the phy_mgmt_clk_reset signal to reset the digital core, analog core, and the PLL core.

xcvr_pll_ref_clk

1

N/A

Input

This signal is present but unused in source-only variations; tie this signal to 1’b0.

user_clock

1

N/A

Input/Output

Clock for data transfers across the source core interface.

  • Input: Using advanced clocking mode
  • Output: Using standard clocking mode
user_clock_reset

1

user_clock

Input/Output

In the standard clocking mode, the core asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete.

In the advanced clocking mode, asserts this signal to reset the adaptation module FIFO buffer.

  • Input: Using advanced clocking mode
  • Output: Using standard clocking mode
interface_clock_reset 1 user_clock Output

Clock for data transfer across the source core interface in the advanced clocking mode.

Available only in Advanced Clocking Mode.

link_up

1

user_clock

Output

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.

data

64xN

user_clock

Input

This vector carries the transmitted streaming data to the core.

N represents the number of lanes.

sync

8

user_clock

Input

The sync vector is an 8 bit bus. The data value at the start of a burst and the end of a burst are captured and transported across the link.

The value at the end of a burst is to indicate the number of invalid 64-bit word in the previous data cycle. As such, for single-lane configuration, the value at the end of a burst is expected to be 0.

Note: This vector is not associated with Interlaken channelization or flow control schemes.
valid

1

user_clock

Input

This single bit signal indicates that the transmitted streaming data is valid.

start_of_burst

1

user_clock

Input

When the core is in burst mode operation, asserting this signal indicates that the information on the data vector is the beginning of a burst.

Because continuous mode is one long burst, in this mode the signal is asserted only once at the start of the data.

end_of_burst

1

user_clock

Input

When the core is in burst mode operation, asserting this signal indicates that the information on the data vector is the end of a burst.

You can optionally send an end of burst signal at the end of continuous mode.

error

4

user_clock

Output

This vector indicates an error or overflow in the source adaptation module’s FIFO buffer.

  • Bit 0: Source adaptation module’s FIFO buffer overflow
  • Bit 1: An SEU error occurred and was corrected (ECC enabled)

    Don't care (ECC disabled)

  • Bit 2: An SEU error occurred and cannot be corrected (ECC enabled)

    Don't care (ECC disabled)

  • Bit 3: A burst gap error occurred due to a mismatch in the BURST GAP parameter value and the gap between end of burst and start of burst.
crc_error_inject 1 user_clock Input This signal forces CRC-32 errors when CRC-32 error injection is enabled in the transceiver channels. The CRC-32 error injection is enabled via the transceiver reconfiguration controller.
Table 29.  Serial Lite III Streaming Arria® 10 and Cyclone® 10 GX IP Core Sink Core Signals

Signal

Width

Clock Domain

Direction

Description

core_reset

1

N/A

Input

Asynchronous master reset for the core. Assert this signal high to reset the MAC layer, except for the I/O PLL that is available in standard clocking mode.

Intel recommends that you tie this signal to the phy_mgmt_clk_reset signal to reset the digital core, analog core, and the PLL core.

xcvr_pll_ref_clk

1

N/A

Input

Reference clock for the transceivers.

user_clock

1

N/A

Output

Clock for data transfers across the sink core interface in the standard clocking mode.

user_clock_reset

1

user_clock

Output

The core asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete in the standard clocking mode.

interface_clock

1

core_clock

Output

Clock for data transfer across the sink core interface in the advanced clocking mode.

interface_clock_reset

1

core_clock

Output

The core asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete.

Available only in Advanced Clocking Mode.

link_up

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.

When this signal is deasserted, all values in the data_rx signal is invalid regardless of the valid_rx signal value. This means even when the valid_rx signal is asserted, the data_rx signal should be treated as invalid when link_up_rx is deasserted.

data

64xN

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector carries the transmitted streaming data from the core.

N represents the number of lanes.

sync

8

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The sync vector is an 8 bit bus that reflects the SYNC value received from the remote partner.

The value at the end of a burst is to indicate the number of invalid 64-bit word in the previous data cycle. As such, for single-lane configuration, the value at the end of a burst is expected to be 0.

Note: This vector is not associated with Interlaken channelization or flow control schemes.
valid

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This single bit signal indicates that the data is valid.

start_of_burst

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

When the core is in burst mode operation, assertion of this signal indicates that the information on the data vector is the beginning of a burst.

Because continuous mode is one long burst, in this mode, the core asserts this signal only once at the start of the data.

end_of_burst

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

When the core is in burst mode operation, assertion of this signal indicates that the information on the data vector is the end of a burst.

error

N+5

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector indicates the state of the sink adaptation module’s FIFO buffer. N represents the number of lanes:

  • [N+4]: An SEU error occurred and cannot be corrected (ECC enabled); Don't care (ECC disabled)

    Don't care (for advanced clocking

  • [N+3]: An SEU error occurred and was corrected (ECC enabled); Don't care (ECC disabled)

    Don't care (for advanced clocking mode)

  • [N+2]: FIFO buffer overflow

    Don't care (for advanced clocking mode)

  • [N+1]: Don't care. Tied to zero.
  • [N]: Loss of alignment
  • [N-1:0]: RX CRC 32 error
Table 30.   Serial Lite III Streaming Arria® 10 and Cyclone® 10 GX IP Core Duplex Core Signals

Signal

Width

Clock Domain

Direction

Description

tx_serial_clk N N/A

Input

This high-speed serial clock input from the external transceiver PLL. The width is the same as the number of lanes specified in the parameter editor. Each bit of the vector corresponds to serial clock of the transmit channel.

N represents the number of lanes.

tx_pll_locked 1 N/A Input This signal indicates that all external transceiver PLLs are locked. If more than one external transceiver PLL is required for higher lanes, each instantiation outputs a bit that indicates whether the PLL providing the high-speed clock for a corresponding transceiver has achieved its lock status. The pll_locked output signal from the external transceiver PLLs should be ANDed together before being input to the IP core.
core_reset

1

N/A

Input

Asynchronous master reset for the core. Assert this signal high to reset the MAC layer, except for the fPLL or I/O PLL that is available in standard clocking mode.

Intel recommends that you tie this signal to the phy_mgmt_clk_reset signal to reset the digital core, analog core, and the PLL core.

xcvr_pll_ref_clk

1

N/A

Input

Reference clock for the transceivers.

user_clock_tx

1

N/A

Input/ Output

Clock for data transfers across the transmit interface.

  • Input: Using advanced clocking mode
  • Output: Using standard clocking mode
user_clock_reset_tx

1

user_clock_tx

Input/ Output

In the standard clocking mode, the core asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete.

In the advanced clocking mode, asserts this signal to reset the adaptation module FIFO buffer.

  • Input: Using advanced clocking mode
  • Output: Using standard clocking mode
interface_clock_reset_tx

1

core_clock

Output

The core asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete.

Available only in Advanced Clocking Mode.

link_up_tx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.

data_tx

64xN

Standard clocking: user_clock

Advanced clocking: core_clock

Input

This vector carries the transmitted streaming data to the core.

N represents the number of lanes.

sync_tx

8

Standard clocking: user_clock

Advanced clocking: core_clock

Input

The sync vector is an 8 bit bus. The data value at the start of a burst and at the end of a burst are captured and transported across the link.

The value at the end of a burst is to indicate the number of invalid 64-bit word in the previous data cycle. As such, for single-lane configuration, the value at the end of a burst is expected to be 0.

Note: This vector is not associated with Interlaken channelization or flow control schemes.
valid_tx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Input

This vector indicates that the data is valid.

start_of_burst_tx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Input

When the core is in burst mode operation, assertion of this signal indicates that the information on the data vector is the beginning of a burst.

Because continuous mode is one long burst, in this mode the signal is asserted only once at the start of the data.

end_of_burst_tx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Input

When the core is in burst mode operation, assertion of this signal indicates that the information on the data vector is the end of a burst.

error_tx

4

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector indicates an overflow in the source adaptation module’s FIFO buffer.

  • Bit 0: Source adaptation module’s FIFO buffer overflow
  • Bit 1: An SEU error occurred and was corrected (ECC enabled).

    Don't care (ECC disabled)

  • Bit 2: An SEU error occurred and cannot be corrected (ECC enabled).

    Don't care (ECC disabled)

  • Bit 3: A burst gap error occurred due to a mismatch in the BURST GAP parameter value and the gap between end of burst and start of burst.
user_clock_rx

1

N/A

Output

Clock for data transfers across the sink core interface in the standard clocking mode.

user_clock_reset_rx

1

user_clock_rx

Output

The core asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete.

Available only in Standard Clocking Mode.

interface_clock_rx

1

core_clock

Output

Clock for data transfers across the sink core interface in the advanced clocking mode.

interface_clock_reset_rx

1

core_clock

Output

The core asserts this signal when the core_reset signal is high and deasserts this signal when the reset sequence is complete.

Available only in Advanced Clocking Mode.

link_up_rx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The core asserts this signal to indicate that the core initialization is complete and is ready to transmit user data.

When this signal is deasserted, all values in the data_rx signal is invalid regardless of the valid_rx signal value. This means even when the valid_rx signal is asserted, the data_rx signal should be treated as invalid when link_up_rx is deasserted.

data_rx

64xN

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector carries the transmitted streaming data from the core.

N represents the number of lanes.

sync_rx

8

Standard clocking: user_clock

Advanced clocking: core_clock

Output

The sync vector is an 8 bit bus that reflects the SYNC value received from the remote partner.

The value at the end of a burst is to indicate the number of invalid 64-bit word in the previous data cycle. As such, for single-lane configuration, the value at the end of a burst is expected to be 0.

Note: This vector is not associated with Interlaken channelization or flow control schemes.
valid_rx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector indicates that the data is valid.

start_of_burst_rx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

When the core is in burst mode operation, asserting this signal indicates that the information on the data vector is the beginning of a burst.

Because continuous mode is one long burst, in this mode the signal is asserted only once at the start of the data.

end_of_burst_rx

1

Standard clocking: user_clock

Advanced clocking: core_clock

Output

When the core is in burst mode operation, asserting this signal indicates that the information on the data vector is the end of a burst.

You can optionally send an end of burst signal at the end of continuous mode.

error _rx

N+5

Standard clocking: user_clock

Advanced clocking: core_clock

Output

This vector indicates the state of the sink adaptation module’s FIFO buffer. N represents the number of lanes:

  • [N+4]: An SEU error occurred and cannot be corrected (ECC enabled); Don't care (ECC disabled)

    Don't care (for advanced clocking mode)

  • [N+3]: An SEU error occurred and was corrected (ECC enabled); Don't care (ECC disabled)

    Don't care (for advanced clocking mode)

  • [N+2]: FIFO buffer overflow

    Don't care (for advanced clocking mode)

  • [N+1]: Don't care. Tied to zero.
  • [N]: Loss of alignment
  • [N-1:0]: RX CRC 32 error
crc_error_inject 1 Standard clocking: user_clock_tx

Advanced clocking: core_clock_tx

Input This signal is used for CRC-32 error injection.
Table 31.  Transceiver Native PHY Arria® 10 and Cyclone® 10 GX IP Core Signals (Interlaken Mode)

Signal

Width

Clock Domain

Direction

Description

phy_mgmt_clk

1

N/A

Input

Clock input for the Avalon memory-mapped PHY management interface within the Native PHY IP core. This signal also clocks the transceiver reconfiguration interface and sequences the reset state machine in the clock generation logic.

phy_mgmt_clk_reset

1

phy_mgmt_clk

Input

Global reset signal that resets the entire IP including MAC, I/O PLL (available in standard clocking mode), and Native PHY IP core. This signal is active high and level sensitive.

phy_mgmt_addr

10 + log2N], N=number of lanes

phy_mgmt_clk

Input

Control and status register (CSR) address for Arria® 10 and Cyclone® 10 GX devices.

The width depends on the number of lanes. The parameter editor determines the required width for you.

You have to manually tie this extra bit 7.

  • phy_mgmt_addr[msb] = 1: for Transceiver reconfiguration usage.
  • phy_mgmt_addr[msb] = 0: for soft CSR (the transceiver reset and loopback control CSR)
phy_mgmt_writedata[31:0]

32

phy_mgmt_clk

Input

CSR write data.

phy_mgmt_readdata[31:0]

32

phy_mgmt_clk

Output

CSR read data.

phy_mgmt_write

1

phy_mgmt_clk

Input

Active high CSR write signal.

phy_mgmt_read

1

phy_mgmt_clk

Input

Active high CSR read signal.

phy_mgmt_waitrequest

1

phy_mgmt_clk

Output

CSR read or write request signal. When asserted, this signal indicates that the Avalon memory-mapped slave interface is unable to respond to a read or write request.

reconfig_busy

1

phy_mgmt_clk

Input

For Arria® 10 and Cyclone® 10 GX devices, this signal is present but unused; tie this signal to 1’b0.

tx_serial_data

N

Output

The serial output data from the core.

N represents the number of lanes.

rx_serial_data

N

Input

The serial input data to the core.

N represents the number of lanes.

7 For more information about this bit, refer to the Interlaken PHY Registers table in the Altera Transceiver PHY IP Core User Guide.