Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

31.3.1. Stream Cleaner IP Interfaces

Table 573.  Stream Cleaner IP Interfaces
Name Direction Width Description
Clocks and resets
main_clock_clk Input 1 AXI4-S processing clock.
main_reset_rst Input 1 AXI4-S processing reset.
Intel FPGA streaming video interfaces
axi4s_vid_in_tdata Input 81 AXI4-S data in.
axi4s_vid_in_tvalid Input 1 AXI4-S data valid.
axi4s_vid_in_tuser[0] Input 1 AXI4-S start of video frame.
axi4s_vid_in_tuser[1] Input 1 AXI4-S control or data packet.
axi4s_vid_in_tuser[N-1:2] Input 82 Unused.
axi4s_vid_in_tlast Input 1 AXI4-S end of packet.
axi4s_vid_in_tready Output 1 AXI4-S data ready.
axi4s_vid_out_tdata Output 81 AXI4-S data in.
axi4s_vid_out_tvalid Output 1 AXI4-S data valid.
axi4s_vid_out_tuser[0] Output 1 AXI4-S start of video frame.
axi4s_vid_out_tuser[1] Output 1 AXI4-S control or data packet.
axi4s_vid_out_tuser[N-1:2] Output 82 Unused.
axi4s_vid_out_tlast Output 1 AXI4-S end of packet.
axi4s_vid_out_tready Input 1 AXI4-S data ready
81

The equation gives all tdata widths sizes in these interfaces:

max (floor(((bits per color sample x number of color planes x pixels in parallel)+ 7) / 8) x 8, 16)

82

This equation gives all tuser widths sizes in these interfaces: N = ceil (tdata width/ 8)