Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

43. Document Revision History for Video and Vision Processing Suite User Guide

Document Version Intel® Quartus® Prime Version Changes
2023.10.02 23.3
  • For the Bits per Color Sample Adapter IP:
    • Added new parameters
    • Added new control interface
    • Added Bits per Color Sample Adapter IP Registers
    • Added Bits per Color Sample Adapter IP Software API
  • Updated bilinear information in Chroma Resampling Functional Description
  • Added new interfaces to Clocked Video Output IP Interfaces
  • Added new interfaces to Video Timing Generator IP Interfaces
2023.06.26 23.2
  • Added new IPs:
    • Bits per Color Sample Adapter IP
    • Video and Vision Monitor IP
    • Video Frame Reader IP
    • Video Frame Writer IP
  • Added weave algorithm to Deinterlacer IP
  • Added Genlock Profiler parameter to Genlock Controller IP.
2023.04.03 23.1
  • Added new Edge behavior parameter to Scaler IP Parameters
  • Added Filter Behavior at Edge Boundaries
  • Updated the product family name to Intel Agilex 7.
  • For the FIR Filter IP:
    • Added new parameter to FIR Filter Parameters
    • Added registers to FIR Filter Registers.
    • Added intel_vvp_fir_runtime_coeffs_load to FIR Filter Software API
  • Updated Warp IP Performance and Resources
2022.12.12 22.4
  • Added new Genlock Controller IP
  • Corrected Clipper register entries 0x148 and 0x14C
  • Corrected example in External Memory for Warp IP.
  • For the clocked Video Input IP:
    • Added new step to Initializing the Clocked Video Input IP
    • Added new f0f1_fps_cnt register
    • Added new APIs.
  • For the FIR Filter IP:
    • Added FIR Filter IP Performance and Resources
    • Changed even to odd in Horizontal Symmetry, Vertical Symmetry and Diagonal Symmetry
  • Added new parameters to the Scaler IP.
  • Added new parameters to the Switch IP and updated registers.
2022.09.30 22.3
  • Added new IPs:
    • Chroma Key IP
    • Interlacer IP
    • Stream Cleaner IP
    • Switch IP
  • Added new 420 and 422 chroma parameters to Scaler IP
  • Added single bounce and block cache tool to Warp IP.
  • Changed some values in FIR Filter Parameters.
  • Changed some values in FIR Filter Precision
  • Corrected IMG_INFO_INTERLACE bits in Deinterlacer Registers
2022.08.08 22.2 Updated description for Deinterlacer IP IMG_INFO_INTERLACE Register
2022.06.25 22.2
  • Added new IPs:
    • AXI-Stream broadcaster
    • Clocked video input
    • Clocked video output
    • Deinterlacer
    • Frame cleaner
    • FIR filter
    • Generic crosspoint
    • Genlock signal router
    • Video timing generator
  • Updated these APIs:
    • Chroma resampler
    • Guard bands
    • Protocol converter
    • Scaler
    • Test pattern generator
    • Video frame buffer
  • Changed Scaler Parameters
2022.04.04 22.1
  • Added new data to Warp IP Performance and Resource Utilization
  • Added Input Resolution Restrictions for 90° or 270° table to Warp IP Block Description
  • Changed Intel Agilex support to final.
  • Updated parameter names in Chroma Resampler Parameters and Scaler Parameters
  • Added interlaced video support to About the Video Frame Buffer.
2022.02.15 21.4
  • Added new IPs:
    • Chroma Resampler
    • Clipper
    • Clocked Video to Streaming Full-Raster Converter
    • Color Space Converter
    • Full-raster to Clocked Video Converter
    • Full-raster to Streaming Converter
    • Guard Bands
    • Mixer
    • Pixel in Parallel Converter
    • Scaler
    • Test Pattern Generator
    • Video Frame Buffer
    • Video Streaming FIFO
    ,
  • Added new APIs to Warp IP
  • Removed two features from Warp IP Features
  • Added new information to Tone Mapping Operator IP:
    • Four new modes
    • New Examples of horizontal slider and region of interest figure
    • Two new register tables
    • New APIs
  • Added Control Examples
  • Added Intel FPGA streaming video full information to Protocol Converter IP
  • Added Easy warp to Warp IP.
2021.09.30 21.3 Added new parameters to 3D LUT IP:
  • Optional output alpha channel
  • LUT sizes of 9³
2021.09.10 21.2 Initial release.