Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 10/02/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide

23.3.1. Genlock Controller IP Interfaces

Table 384.   Genlock Controller IP Interfaces
Name Direction Width Description
Clocks and Resets
vcxo_clock Input 1 Input VCXO clock
vcxo_reset Input 1 Input VCXO reset
ref0_clock Input 1 Input reference # 0 clock
ref0_reset Input 1 Input reference # 0 reset
ref1_clock Input 1 Input reference # 1 clock
ref1_reset Input 1 Input reference # 1 reset
ref2_clock Input 1 Input reference # 2 clock
ref2_reset Input 1 Input reference # 2 reset
ref3_clock Input 1 Input reference # 3 clock
ref3_reset Input 1 Input reference # 3 reset
cpu_clock Input 1 Control interface clock
cpu_reset Input 1 Control interface reset
Control Interfaces
av_mm_control_agent_address Input 7 Avalon memory-mapped agent address
av_mm_control_agent_write Input 1 Avalon memory-mapped agent write
av_mm_control_agent_writedata Input 32 Avalon memory-mapped agent write data
av_mm_control_agent_byteenable Input 4 Avalon memory-mapped agent byte enable
av_mm_control_agent_read Input 1 Avalon memory-mapped agent read request
av_mm_control_agent_readdata Output 32 Avalon memory-mapped agent read data
av_mm_control_agent_readdatavalid Output 1 Avalon memory-mapped agent read valid
av_mm_control_agent_waitrequest Output 1 Avalon memory-mapped agent wait request
External Output Conduits
vcxo pwm Output 1 A three-state PWM output to control an external VCXO
locked Output 1 A level signal indicating if the IP achieves the genlock between the reference clock and VCXO.
Genlock Profiler Input Conduits
vid_rx_ref_tim Input 1 Receive toggle SOF signal
vid_tx_ref_tim Input 1 Transmit toggle SOF signal
Genlock Profiler Output Conduits
GPO bus Output 8 Genlock error mapping general purpose output (GPO) bus