Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 10/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Bits per Color Sample Adapter Intel FPGA IP 11. Chroma Key Intel® FPGA IP 12. Chroma Resampler Intel® FPGA IP 13. Clipper Intel® FPGA IP 14. Clocked Video Input Intel® FPGA IP 15. Clocked Video to Full-Raster Converter Intel® FPGA IP 16. Clocked Video Output Intel® FPGA IP 17. Color Space Converter Intel® FPGA IP 18. Deinterlacer Intel® FPGA IP 19. FIR Filter Intel® FPGA IP 20. Frame Cleaner Intel® FPGA IP 21. Full-Raster to Clocked Video Converter Intel® FPGA IP 22. Full-Raster to Streaming Converter Intel® FPGA IP 23. Genlock Controller Intel® FPGA IP 24. Generic Crosspoint Intel® FPGA IP 25. Genlock Signal Router Intel® FPGA IP 26. Guard Bands Intel® FPGA IP 27. Interlacer Intel® FPGA IP 28. Mixer Intel® FPGA IP 29. Pixels in Parallel Converter Intel® FPGA IP 30. Scaler Intel® FPGA IP 31. Stream Cleaner Intel® FPGA IP 32. Switch Intel® FPGA IP 33. Tone Mapping Operator Intel® FPGA IP 34. Test Pattern Generator Intel® FPGA IP 35. Video and Vision Monitor Intel FPGA IP 36. Video Frame Buffer Intel® FPGA IP 37. Video Frame Reader Intel FPGA IP 38. Video Frame Writer Intel FPGA IP 39. Video Streaming FIFO Intel® FPGA IP 40. Video Timing Generator Intel® FPGA IP 41. Warp Intel® FPGA IP 42. Design Security 43. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Bits per Color Sample Adapter Intel FPGA IP x
10.1. About the Bits per Color Sample Adapter IP 10.2. Bits per Color Sample Adapter IP Parameters 10.3. Bits per Color Sample Adapter IP Interfaces 10.4. Bits per Color Sample Adapter IP Registers 10.5. Bits per Color Sample Adapter Software API
10.1. About the Bits per Color Sample Adapter IP x
10.1.1. Bits per Color Sample Adapter IP Performance and Resources
11. Chroma Key Intel® FPGA IP x
11.1. About the Chroma Key IP 11.2. Chroma Key IP Parameters 11.3. Chroma Key IP Interfaces 11.4. Chroma Key Replacement 11.5. Chroma Key IP Registers 11.6. Chroma Key IP Software API
11.1. About the Chroma Key IP x
11.1.1. Chroma Key IP Performance and Resources
12. Chroma Resampler Intel® FPGA IP x
12.1. About the Chroma Resampler IP 12.2. Chroma Resampler IP Parameters 12.3. Chroma Resampler IP Functional Description 12.4. Chroma Resampler IP Registers 12.5. Chroma Resampler IP Software API
12.1. About the Chroma Resampler IP x
12.1.1. Chroma Resampler Performance and Resources
12.3. Chroma Resampler IP Functional Description x
12.3.1. Chroma Resampler IP Interfaces
13. Clipper Intel® FPGA IP x
13.1. About the Clipper IP 13.2. Clipper IP Parameters 13.3. Clipper IP Interfaces 13.4. Clipper IP Registers 13.5. Clipper IP Software API
13.1. About the Clipper IP x
13.1.1. Clipper IP Performance and Resources
14. Clocked Video Input Intel® FPGA IP x
14.1. About the Clocked Video Input IP 14.2. Initializing the Clocked Video Input IP 14.3. Clocked Video Input IP Parameters 14.4. Clocked Video Input IP Interfaces 14.5. Clocked Video Input IP Registers 14.6. Clocked Video Input IP Software API
14.1. About the Clocked Video Input IP x
14.1.1. Clocked Video Input IP Features 14.1.2. Clocked Video Input IP Performance and Resources
15. Clocked Video to Full-Raster Converter Intel® FPGA IP x
15.1. About the Clocked Video to Full-Raster Converter IP 15.2. Clocked Video to Full-Raster Converter Parameters 15.3. Clocked Video to Full-Raster Converter Block Description 15.4. Clocked Video Converter to Full-Raster IP Registers
15.1. About the Clocked Video to Full-Raster Converter IP x
15.1.1. Clocked Video to Full-Raster Converter Features 15.1.2. Clocked Video to Full-Raster Converter Performance and Resources
15.3. Clocked Video to Full-Raster Converter Block Description x
15.3.1. Clocked Video to Full-Raster Converter Interfaces
16. Clocked Video Output Intel® FPGA IP x
16.1. About the Clocked Video Output IP 16.2. Clocked Video Output IP Parameters 16.3. Clocked Video Output IP Functional Description 16.4. Clocked Video Output IP Interfaces 16.5. Clocked Video Output IP Registers 16.6. Clocked Video Output IP Software API
16.1. About the Clocked Video Output IP x
16.1.1. Clocked Video Output IP Performance and Resources 16.1.2. Clocked Video Output IP Features
17. Color Space Converter Intel® FPGA IP x
17.1. About the Color Space Converter IP 17.2. Color Space Converter IP Parameters 17.3. Color Space Converter IP Functional Description 17.4. Color Space Converter IP Registers 17.5. Color Space Converter IP Software API
17.1. About the Color Space Converter IP x
17.1.1. Color Space Converter IP Features 17.1.2. Color Space Converter IP Performance and Resources
17.3. Color Space Converter IP Functional Description x
17.3.1. Color Space Converter IP Interfaces
18. Deinterlacer Intel® FPGA IP x
18.1. About the Deinterlacer IP 18.2. Deinterlacer Parameters 18.3. Deinterlacer Interfaces 18.4. Deinterlacer IP Registers 18.5. Deinterlacer IP Software API
18.1. About the Deinterlacer IP x
18.1.1. Deinterlacer Performance and Resources
19. FIR Filter Intel® FPGA IP x
19.1. About the FIR Filter 19.2. FIR Filter Parameters 19.3. FIR Filter IP Operation 19.4. FIR Filter Interfaces 19.5. FIR Filter Registers 19.6. FIR Filter IP Software API
19.1. About the FIR Filter x
19.1.1. FIR Filter IP Performance and Resources
19.3. FIR Filter IP Operation x
19.3.1. FIR Filter Processing 19.3.2. FIR Filter Precision 19.3.3. FIR Coefficient Specification 19.3.4. FIR Filter Symmetry 19.3.5. Result to Output Data Type Conversion
19.3.4. FIR Filter Symmetry x
19.3.4.1. No Symmetry 19.3.4.2. Horizontal Symmetry 19.3.4.3. Vertical Symmetry 19.3.4.4. Horizontal and Vertical Symmetry 19.3.4.5. Diagonal Symmetry
20. Frame Cleaner Intel® FPGA IP x
20.1. About the Frame Cleaner IP 20.2. Frame Cleaner IP Parameters 20.3. Frame Cleaner IP Functional Description 20.4. Frame Cleaner IP Interfaces 20.5. Frame Cleaner IP Registers 20.6. Frame Cleaner IP Software API
20.1. About the Frame Cleaner IP x
20.1.1. Frame Cleaner IP Performance and Resources
21. Full-Raster to Clocked Video Converter Intel® FPGA IP x
21.1. About the Full-Raster to Clocked Video Converter 21.2. Full Raster to Clocked Video Converter Parameters 21.3. Full-Raster to Clocked Video Converter Block Description 21.4. Full-Raster to Clocked Video Converter Registers
21.1. About the Full-Raster to Clocked Video Converter x
21.1.1. Full-Raster to Clocked Video Converter Features 21.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
21.3. Full-Raster to Clocked Video Converter Block Description x
21.3.1. Full Raster to Clocked Video Converter Interfaces
22. Full-Raster to Streaming Converter Intel® FPGA IP x
22.1. About the Full-Raster to Streaming Converter IP 22.2. Full-Raster to Streaming Converter Parameters 22.3. Full-Raster to Streaming Converter Block Description
22.1. About the Full-Raster to Streaming Converter IP x
22.1.1. Full-Raster to Streaming Converter Features 22.1.2. Full-Raster to Streaming Converter Performance and Resources
22.3. Full-Raster to Streaming Converter Block Description x
22.3.1. Full-Raster to Streaming Converter Interfaces
23. Genlock Controller Intel® FPGA IP x
23.1. About the Genlock Controller IP 23.2. Genlock Controller IP Parameters 23.3. Genlock Controller IP Functional Description 23.4. Using Genlock Controller IP Software 23.5. Genlock Controller IP Registers 23.6. Genlock Controller IP Software API
23.1. About the Genlock Controller IP x
23.1.1. Genlock Controller IP Performance and Resources
23.3. Genlock Controller IP Functional Description x
23.3.1. Genlock Controller IP Interfaces
23.4. Using Genlock Controller IP Software x
23.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 23.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 23.4.3. Setting the VCXO hold over 23.4.4. Restarting the Genlock Controller IP 23.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 23.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 23.4.7. Disturbing a Reference Clock (a cable pull)
24. Generic Crosspoint Intel® FPGA IP x
24.1. About the Generic Crosspoint IP 24.2. Generic Crosspoint IP Parameters 24.3. Generic Crosspoint IP Interfaces 24.4. Generic Crosspoint IP Registers 24.5. Generic Crosspoint IP Software API
24.1. About the Generic Crosspoint IP x
24.1.1. Generic Crosspoint IP Features 24.1.2. Generic Crosspoint Performance and Resources
25. Genlock Signal Router Intel® FPGA IP x
25.1. About the Genlock Signal Router IP 25.2. Genlock Signal Router IP Parameters 25.3. Genlock Signal Router IP Interfaces 25.4. Genlock Signal Router IP Registers 25.5. Genlock Signal Router IP Software API
25.1. About the Genlock Signal Router IP x
25.1.1. Genlock Signal Router IP Features 25.1.2. Genlock Signal Router IP Performance and Resources
26. Guard Bands Intel® FPGA IP x
26.1. About the Guard Bands IP 26.2. Guard Bands IP Parameters 26.3. Guard Bands IP Interfaces 26.4. Guard Bands IP Registers 26.5. Guard Bands IP Software API
26.1. About the Guard Bands IP x
26.1.1. Guard Bands IP Performance and Resources
27. Interlacer Intel® FPGA IP x
27.1. About the Interlacer IP 27.2. Interlacer IP Parameters 27.3. Interlacer IP Functional Description 27.4. Interlacer IP Registers 27.5. Interlacer IP Software API
27.1. About the Interlacer IP x
27.1.1. Interlacer IP Performance and Resources
27.3. Interlacer IP Functional Description x
27.3.1. Interlacer IP Interfaces
28. Mixer Intel® FPGA IP x
28.1. About the Mixer IP 28.2. Mixer IP Parameters 28.3. Mixer IP Functional Description 28.4. Mixer IP Registers 28.5. Mixer IP Software API
28.1. About the Mixer IP x
28.1.1. Mixer IP Performance and Resources
28.3. Mixer IP Functional Description x
28.3.1. Mixer IP Interfaces
29. Pixels in Parallel Converter Intel® FPGA IP x
29.1. About the Pixels in Parallel Converter IP 29.2. Pixels in Parallel Converter IP Parameters 29.3. Pixels in Parallel Converter Interfaces 29.4. Pixels in Parallel Converter Registers 29.5. Pixels in Parallel Converter IP Software API
29.1. About the Pixels in Parallel Converter IP x
29.1.1. Pixels in Parallel Converter IP Performance and Resources
30. Scaler Intel® FPGA IP x
30.1. About the Scaler 30.2. Scaler IP Parameters 30.3. Scaler IP Functional Description 30.4. Scaler IP Registers 30.5. Scaler IP Software API
30.1. About the Scaler x
30.1.1. Scaler IP Performance and Resources
30.2. Scaler IP Parameters x
30.2.1. Scaler Maximum Resolution
30.3. Scaler IP Functional Description x
30.3.1. Coefficient Selection 30.3.2. Coefficient Quantization 30.3.3. Filter Behavior at Edge Boundaries 30.3.4. Partial Frame Scaling 30.3.5. 422 and 420 Chroma Sampled Data Scaling 30.3.6. Scaler IP Interfaces
30.3.1. Coefficient Selection x
30.3.1.1. Updating Scaler IP Runtime Coefficients
31. Stream Cleaner Intel® FPGA IP x
31.1. About the Stream Cleaner IP 31.2. Stream Cleaner IP Parameters 31.3. Stream Cleaner IP Functional Description
31.1. About the Stream Cleaner IP x
31.1.1. Stream Cleaner IP Performance and Resources
31.3. Stream Cleaner IP Functional Description x
31.3.1. Stream Cleaner IP Interfaces
32. Switch Intel® FPGA IP x
32.1. About the Switch IP 32.2. Switch IP Parameters 32.3. Switch IP Functional Description 32.4. Switch IP Registers 32.5. Switch IP Software API
32.1. About the Switch IP x
32.1.1. Switch IP Performance and Resources
32.3. Switch IP Functional Description x
32.3.1. Switch IP Latency 32.3.2. Switch IP Interfaces
33. Tone Mapping Operator Intel® FPGA IP x
33.1. About the Tone Mapping Operator IP 33.2. TMO IP Parameters 33.3. TMO IP Block Description 33.4. TMO IP Registers 33.5. TMO IP Software API
33.1. About the Tone Mapping Operator IP x
33.1.1. TMO IP Features 33.1.2. TMO IP Performance and Resource Utilization
33.3. TMO IP Block Description x
33.3.1. TMO IP Interfaces 33.3.2. TMO IP Latency
34. Test Pattern Generator Intel® FPGA IP x
34.1. About the Test Pattern Generator IP 34.2. Test Pattern Generator IP Parameters 34.3. Test Pattern Generator IP Functional Description 34.4. Test Pattern Generator IP Registers 34.5. Test Pattern Generator IP Software API
34.1. About the Test Pattern Generator IP x
34.1.1. Test Pattern Generator IP Performance and Resources
34.3. Test Pattern Generator IP Functional Description x
Bars pattern Constant color SDI Pathological Output subsampling and color space Updating settings at run time Full Variants Lite mode 34.3.1. Test Pattern Generator IP Interfaces
35. Video and Vision Monitor Intel FPGA IP x
35.1. About the Video and Vision Monitor IP 35.2. Video and Vision Monitor IP Parameters 35.3. Video and Vision Monitor IP Functional Description 35.4. Video and Vision Monitor IP Registers 35.5. Video and Vision Monitor Software API
35.1. About the Video and Vision Monitor IP x
35.1.1. Video and Vision Monitor IP Performance and Resources
35.3. Video and Vision Monitor IP Functional Description x
35.3.1. Video and Vision Monitor IP Interfaces
36. Video Frame Buffer Intel® FPGA IP x
36.1. About the Video Frame Buffer IP 36.2. Video Frame Buffer IP Parameters 36.3. Video Frame Buffer IP Functional Description 36.4. Video Frame Buffer IP Registers 36.5. Video Frame Buffer IP Software API
36.1. About the Video Frame Buffer IP x
36.1.1. Video Frame Buffer Performance and Resources
36.3. Video Frame Buffer IP Functional Description x
36.3.1. Video Frame Buffer IP Interfaces
37. Video Frame Reader Intel FPGA IP x
37.1. About the Video Frame Reader IP 37.2. Video Frame Reader IP Parameters 37.3. Video Frame Reader IP Functional Description 37.4. Video Frame Reader IP Registers 37.5. Video Frame Reader IP Software API
37.1. About the Video Frame Reader IP x
37.1.1. Video Frame Reader IP Performance and Resources
37.3. Video Frame Reader IP Functional Description x
37.3.1. Video Frame Reader IP Interfaces
38. Video Frame Writer Intel FPGA IP x
38.1. About the Video Buffer Writer IP 38.2. Video Frame Writer IP Parameters 38.3. Video Frame Writer IP Functional Description 38.4. Video Frame Writer IP Registers 38.5. Video Frame Writer IP Software API
38.1. About the Video Buffer Writer IP x
38.1.1. Video Frame Writer IP Performance and Resources
38.3. Video Frame Writer IP Functional Description x
38.3.1. Video Frame Writer IP Interfaces
39. Video Streaming FIFO Intel® FPGA IP x
39.1. About the Video Streaming FIFO IP 39.2. Video Streaming FIFO IP Parameters 39.3. Video Streaming FIFO IP Interfaces
39.1. About the Video Streaming FIFO IP x
39.1.1. Video Streaming FIFO IP Performance and Resources
40. Video Timing Generator Intel® FPGA IP x
40.1. About the Video Timing Generator IP 40.2. Video Timing Generator IP Parameters 40.3. Video Timing Generator IP Functional Description 40.4. Video Timing Generator IP Interfaces 40.5. Video Timing Generator IP Registers 40.6. Video Timing Generator IP Software API
40.1. About the Video Timing Generator IP x
40.1.1. Video Timing Generator IP Features 40.1.2. Video Timing Generator IP Performance and Resources
41. Warp Intel® FPGA IP x
41.1. About the Warp IP 41.2. Warp IP Parameters 41.3. Warp IP Block Description 41.4. Warp IP Registers 41.5. Warp IP Software API
41.1. About the Warp IP x
41.1.1. Warp IP Features 41.1.2. Warp IP Performance and Resource Utilization
41.3. Warp IP Block Description x
41.3.1. Block Cache Tool 41.3.2. Warp IP Interfaces 41.3.3. Warp IP Latency 41.3.4. External Memory for Warp IP
41.5. Warp IP Software API x
41.5.1. Using Warp IP Software 41.5.2. Warp IP Software Code Examples
42. Design Security x
42.1. Memory Subsystems 42.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Bits per Color Sample Adapter Intel FPGA IP
11. Chroma Key Intel® FPGA IP
12. Chroma Resampler Intel® FPGA IP
13. Clipper Intel® FPGA IP
14. Clocked Video Input Intel® FPGA IP
15. Clocked Video to Full-Raster Converter Intel® FPGA IP
16. Clocked Video Output Intel® FPGA IP
17. Color Space Converter Intel® FPGA IP
18. Deinterlacer Intel® FPGA IP
19. FIR Filter Intel® FPGA IP
20. Frame Cleaner Intel® FPGA IP
21. Full-Raster to Clocked Video Converter Intel® FPGA IP
22. Full-Raster to Streaming Converter Intel® FPGA IP
23. Genlock Controller Intel® FPGA IP
24. Generic Crosspoint Intel® FPGA IP
25. Genlock Signal Router Intel® FPGA IP
26. Guard Bands Intel® FPGA IP
27. Interlacer Intel® FPGA IP
28. Mixer Intel® FPGA IP
29. Pixels in Parallel Converter Intel® FPGA IP
30. Scaler Intel® FPGA IP
31. Stream Cleaner Intel® FPGA IP
32. Switch Intel® FPGA IP
33. Tone Mapping Operator Intel® FPGA IP
34. Test Pattern Generator Intel® FPGA IP
35. Video and Vision Monitor Intel FPGA IP
36. Video Frame Buffer Intel® FPGA IP
37. Video Frame Reader Intel FPGA IP
38. Video Frame Writer Intel FPGA IP
39. Video Streaming FIFO Intel® FPGA IP
40. Video Timing Generator Intel® FPGA IP
41. Warp Intel® FPGA IP
42. Design Security
43. Document Revision History for Video and Vision Processing Suite User Guide

34.3. Test Pattern Generator IP Functional Description

The Test Pattern Generator Intel FPGA IP enables you to choose between different test patterns, either at run time or compile time.
  • Bars pattern
    • Color bars
    • Grayscale bars
    • Black and white bars
    • Mixed bars
  • Constant color
  • SDI pathological

Bars pattern

If you select Bars Pattern, the IP produces a test pattern with 8 vertical bars, each covering approximately 1/8th of each output video line. The bars contain either a sequence of changing colors (color bars), a sequence of greyscale tones with decreasing brightness (greyscale bars), or a sequence of alternating black and white bars. Mixed bars change the pattern in the vertical direction, with the first 1/8th of the lines showing the black and white bars, the next 1/8th showing the greyscale bars, and the final ¾ showing the color bars. If you select bars pattern (and turn on the Avalon memory-mapped control agent interface), a value in the register map selects at run time which variant of the bars pattern to display. If you do not turn on Avalon memory-mapped control agent, the fixed bars mode parameter controls which variant of the bars pattern to display, and you cannot change it at run time.

For all test patterns, each bar is approximately 1/8th of the width of the output frame, but this width is not exact. The actual width of each color bar is affected by the field width and the horizontal subsampling.

When the width of the field is not divisible by eight, the remainder pixels from the division are spread as evenly as possible across the bars. The first bar, on the left-hand side of the field, always has floor(field_width/8) pixels. A single remainder pixel is added to the width of each subsequent bar until all the remainder pixels are exhausted. The width of each bar cannot be less than the number of pixels transmitted per beat at the output interface (pixels in parallel). If the field width is set to less than 8 x pixels in parallel, as many bars as possible display with pixels in parallel pixels per bar, but fewer than 8 bars display. When the output is horizontally subsampled (4:2:2 or 4:2:0), the pixel-width of each color bar is a multiple of two and we alter the methods described above to ensure this is always the case.

The tables define the values of the color components in each bar for each of the three basic modes. The values are the actual output values if you set bits per color plane to 8 bits. If bits per color is greater than 8 bits, the internal logic upshifts the value by the required number of bits, with zeros added in the LSBs.

Table 616.  Output values for each color plane in both the RGB and YCbCr color spaces for the color bars test pattern
Color RGB YCbCr
White (left) (180, 180, 180) (180, 128, 128)
Yellow (180, 180, 16) (162, 44, 142)
Cyan (16, 180, 180) (131, 156, 44)
Green (16, 180, 16) (112, 72, 58)
Magenta (180, 16, 180) (84, 184, 198)
Red (180, 16, 16) (65, 100, 212)
Blue (16, 16, 180) (35, 212, 114)
Black (right) (16, 16, 16) (16, 128, 128)
Table 617.   Output values for each color plane in both the RGB and YCbCr color spaces for the greyscale bars test pattern
Color RGB YCbCr
0 (left) (180, 180, 180) (180, 128, 128)
1 (162, 162, 162) (162, 128, 128)
2 (131, 131, 131) (131, 128, 128)
3 (112, 112, 112) (112, 128, 128)
4 (84, 84, 84) (84, 128, 128)
5 (65, 65, 65) (65, 128, 128)
6 (35, 35, 35) (35, 128, 128)
7 (right) (16, 16, 16) (16, 128, 128)
Table 618.  Output values for each color plane in both the RGB and YCbCr color spaces for the black and white bars test pattern
Color RGB YCbCr
0 (left) (180, 180, 180) (180, 128, 128)
1 (16, 16, 16) (16, 128, 128)
2 (180, 180, 180) (180, 128, 128)
3 (16, 16, 16) (16, 128, 128)
4 (180, 180, 180) (180, 128, 128)
5 (16, 16, 16) (16, 128, 128)
6 (180, 180, 180) (180, 128, 128)
7 (right) (16, 16, 16) (16, 128, 128)

Constant color

The constant color test pattern is a complete field or frame of a constant color. This test pattern has limited value for testing, but you can use the pattern to form a background layer for a mixer. Set the RGB or YCbCr values for the desired color as either fixed, compile-time-set parameters or run-time controlled values through the Avalon memory-mapped control agent interface.

SDI Pathological

The SDI pathological test pattern is specifically designed to stress test the SDI equalizer and PLL performance. The test pattern consists of a static test image with the top half of the lines filled with a shade of magenta, and the bottom half of the lines filled with a shade of gray.

Output subsampling and color space

You can configure the output subsampling and color space to either be fixed and set at compile time, or to be variable at run time using the Avalon memory-mapped control agent interface.

The Output Format parameter sets the subsampling option:

  • 4:4:4. Output is fixed at full sampling for each color plane (can be RGB or YCbCr). Each pixel has 3 color planes.
  • 4:2:2. Output is fixed at full sampling on the Y plane and horizontal subsampling on the Cb and Cr planes (RGB data is not supported in 4:2:2 mode). Each pixel has 2 color planes.
  • 4:2:0. Output is fixed at full sampling on the Y plane and horizontal and vertical subsampling on the Cb and Cr planes (RGB data is not supported in 4:2:0 mode). Each pixel has 3 color planes.
  • Monochrome. Output has only 1 color plane per pixel and represents only a fully sampled Y plane.
  • Variable. Output can be configured at run time to be 4:4:4 RGB, 4:4:4 YCbCr, 4:2:2 YCbCr, or 4:2:0 YCbCr. Each pixel has 3 color planes.

The IP allows you to select up to 8 different test pattern configurations to switch between at run time:

  • Each configuration is a combination of 1 of the 3 available patterns and a formatting option.
  • Each test pattern configuration is fixed in one particular output format. However, by selecting between the patterns, you can vary the overall output format at run time.

For example, you may include 4 different configurations, all of which use the bars pattern, but with the first configuration set to 4:4:4 RGB, the second set to 4:4:4 YCbCr, the third set to 4:2:2 YCbCr, and the fourth set to 4:2:0 YCbCr. With this setting, you can validate all the possible configurations of an HDMI 2.0 output.

Updating settings at run time

If you turn on the Avalon memory-mapped control agent interface, the resolution, interlace settings and test pattern configuration can be adjusted at run time via the register map. The model for executing settings changes at run time differs depending on whether the test pattern generator is parameterized to output the full or lite variant of the Intel FPGA streaming video protocol.

Full Variants

When you turn off Lite mode, you can edit any of the test pattern generator settings at any time. The IP does not apply the settings until the start of the next frame after a write to the COMMIT register (address 0x014C). The IP can complete a change to the settings that requires writes to multiple registers without the risk of applying the earlier writes in the sequence one frame before the later writes in the sequence.

The full sequence for register updates for full variants is:

  1. Make the required edits to any subset of the test pattern generator settings in the register map (addresses 0x120 to 0x0128 and addresses 0x0150 and 0x015C to 0x0168).
  2. After the first write to update a setting, the IP asserts bit 1 of the STATUS register (address 0x0140) in the return data for any read to this address.
  3. Write any value to the COMMIT register (address 0x014C) to commit the changes as a coherent set.
  4. Do not make any further edits to the settings until the IP deasserts bit 1 of the STATUS register at the next field boundary after the write to the COMMIT register. If the IP has any updates to the test pattern settings (address 0x0120 to 0x0128, and 0x0150), at this point the field index is reset to 0. The field index is a count of the number of frames since the last update. The interlace sequence is reset to start at F0 or F1, as specified in the register map.
  5. When the IP deasserts bit 1 of the STATUS register, you may make further settings updates.

The COMMIT mode register gates the application of updates to all registers except the CONTROL register (address 0x0148). The CONTROL register allows you to stop and start the IP output at frame boundaries. The IP applies updates to the CONTROL register at the next field boundary, regardless of whether you write to the COMMIT register.

Lite mode

If you turn on Lite mode the IP has no COMMIT register functionality. The recommended flow for updating the test pattern generator settings is:

  1. Write 0 to the CONTROL register (address 0x0148) to stop the test pattern generator at the next field boundary.
  2. Read the STATUS register (address 0x0140) until bit 0 is de-asserted, indicating that the test pattern generator is in an idle state between fields.
  3. Make the required edits to any subset of the test pattern generator settings in the register map (addresses 0x120 to 0x0128 and addresses 0x0150 and 0x015C to 0x0168).
  4. Write 1 to the CONTROL register to restart the test pattern generator with the new settings. If the IP has any updates to the test pattern settings (address 0x0120 to 0x0128, and 0x0150), at this point the field index is reset to 0. The interlace sequence is reset to start at F0 or F1, as specified in the register map.

Section Content
Test Pattern Generator IP Interfaces

Level Two Title