Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 12/12/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Key Intel® FPGA IP x
10.1. About the Chroma Key IP 10.2. Chroma Key IP Parameters 10.3. Chroma Key IP Interfaces 10.4. Chroma Key Replacement 10.5. Chroma Key IP Registers 10.6. Chroma Key IP Software API
10.1. About the Chroma Key IP x
10.1.1. Chroma Key IP Performance and Resources
11. Chroma Resampler Intel® FPGA IP x
11.1. About the Chroma Resampler IP 11.2. Chroma Resampler IP Parameters 11.3. Chroma Resampler IP Functional Description 11.4. Chroma Resampler IP Registers 11.5. Chroma Resampler IP Software API
11.1. About the Chroma Resampler IP x
11.1.1. Chroma Resampler Performance and Resources
11.3. Chroma Resampler IP Functional Description x
11.3.1. Chroma Resampler IP Interfaces
12. Clipper Intel® FPGA IP x
12.1. About the Clipper IP 12.2. Clipper IP Parameters 12.3. Clipper IP Interfaces 12.4. Clipper IP Registers 12.5. Clipper IP Software API
12.1. About the Clipper IP x
12.1.1. Clipper IP Performance and Resources
13. Clocked Video Input Intel® FPGA IP x
13.1. About the Clocked Video Input IP 13.2. Initializing the Clocked Video Input IP 13.3. Clocked Video Input IP Parameters 13.4. Clocked Video Input IP Interfaces 13.5. Clocked Video Input IP Registers 13.6. Clocked Video Input IP Software API
13.1. About the Clocked Video Input IP x
13.1.1. Clocked Video Input IP Features 13.1.2. Clocked Video Input IP Performance and Resources
14. Clocked Video to Full-Raster Converter Intel® FPGA IP x
14.1. About the Clocked Video to Full-Raster Converter IP 14.2. Clocked Video to Full-Raster Converter Parameters 14.3. Clocked Video to Full-Raster Converter Block Description 14.4. Clocked Video Converter to Full-Raster IP Registers
14.1. About the Clocked Video to Full-Raster Converter IP x
14.1.1. Clocked Video to Full-Raster Converter Features 14.1.2. Clocked Video to Full-Raster Converter Performance and Resources
14.3. Clocked Video to Full-Raster Converter Block Description x
14.3.1. Clocked Video to Full-Raster Converter Interfaces
15. Clocked Video Output Intel® FPGA IP x
15.1. About the Clocked Video Output IP 15.2. Clocked Video Output IP Parameters 15.3. Clocked Video Output IP Functional Description 15.4. Clocked Video Output IP Interfaces 15.5. Clocked Video Output IP Registers 15.6. Clocked Video Output IP Software API
15.1. About the Clocked Video Output IP x
15.1.1. Clocked Video Output IP Performance and Resources 15.1.2. Clocked Video Output IP Features
16. Color Space Converter Intel® FPGA IP x
16.1. About the Color Space Converter IP 16.2. Color Space Converter IP Parameters 16.3. Color Space Converter IP Functional Description 16.4. Color Space Converter IP Registers 16.5. Color Space Converter IP Software API
16.1. About the Color Space Converter IP x
16.1.1. Color Space Converter IP Features 16.1.2. Color Space Converter IP Performance and Resources
16.3. Color Space Converter IP Functional Description x
16.3.1. Color Space Converter IP Interfaces
17. Deinterlacer Intel® FPGA IP x
17.1. About the Deinterlacer IP 17.2. Deinterlacer Parameters 17.3. Deinterlacer Interfaces 17.4. Deinterlacer Registers 17.5. Deinterlacer IP Software API
17.1. About the Deinterlacer IP x
17.1.1. Deinterlacer Performance and Resources
18. FIR Filter Intel® FPGA IP x
18.1. About the FIR Filter 18.2. FIR Filter Parameters 18.3. FIR Filter IP Operation 18.4. FIR Filter Interfaces 18.5. FIR Filter Registers 18.6. FIR Filter IP Software API
18.1. About the FIR Filter x
18.1.1. FIR Filter IP Performance and Resources
18.3. FIR Filter IP Operation x
18.3.1. FIR Filter Processing 18.3.2. FIR Filter Precision 18.3.3. FIR Coefficient Specification 18.3.4. FIR Filter Symmetry 18.3.5. Result to Output Data Type Conversion
18.3.4. FIR Filter Symmetry x
18.3.4.1. No Symmetry 18.3.4.2. Horizontal Symmetry 18.3.4.3. Vertical Symmetry 18.3.4.4. Horizontal and Vertical Symmetry 18.3.4.5. Diagonal Symmetry
19. Frame Cleaner Intel® FPGA IP x
19.1. About the Frame Cleaner IP 19.2. Frame Cleaner IP Parameters 19.3. Frame Cleaner IP Functional Description 19.4. Frame Cleaner IP Interfaces 19.5. Frame Cleaner IP Registers 19.6. Frame Cleaner IP Software API
19.1. About the Frame Cleaner IP x
19.1.1. Frame Cleaner IP Performance and Resources
20. Full-Raster to Clocked Video Converter Intel® FPGA IP x
20.1. About the Full-Raster to Clocked Video Converter 20.2. Full Raster to Clocked Video Converter Parameters 20.3. Full-Raster to Clocked Video Converter Block Description 20.4. Full-Raster to Clocked Video Converter Registers
20.1. About the Full-Raster to Clocked Video Converter x
20.1.1. Full-Raster to Clocked Video Converter Features 20.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
20.3. Full-Raster to Clocked Video Converter Block Description x
20.3.1. Full Raster to Clocked Video Converter Interfaces
21. Full-Raster to Streaming Converter Intel® FPGA IP x
21.1. About the Full-Raster to Streaming Converter IP 21.2. Full-Raster to Streaming Converter Parameters 21.3. Full-Raster to Streaming Converter Block Description
21.1. About the Full-Raster to Streaming Converter IP x
21.1.1. Full-Raster to Streaming Converter Features 21.1.2. Full-Raster to Streaming Converter Performance and Resources
21.3. Full-Raster to Streaming Converter Block Description x
21.3.1. Full-Raster to Streaming Converter Interfaces
22. Genlock Controller Intel® FPGA IP x
22.1. About the Genlock Controller IP 22.2. Genlock Controller IP Parameters 22.3. Genlock Controller IP Functional Description 22.4. Using Genlock Controller IP Software 22.5. Genlock Controller IP Registers 22.6. Genlock Controller IP Software API
22.1. About the Genlock Controller IP x
22.1.1. Genlock Controller IP Performance and Resources
22.3. Genlock Controller IP Functional Description x
22.3.1. Genlock Controller IP Interfaces
22.4. Using Genlock Controller IP Software x
22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 22.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 22.4.3. Setting the VCXO hold over 22.4.4. Restarting the Genlock Controller IP 22.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 22.4.7. Disturbing a Reference Clock (a cable pull)
23. Generic Crosspoint Intel® FPGA IP x
23.1. About the Generic Crosspoint IP 23.2. Generic Crosspoint IP Parameters 23.3. Generic Crosspoint IP Interfaces 23.4. Generic Crosspoint IP Registers 23.5. Generic Crosspoint IP Software API
23.1. About the Generic Crosspoint IP x
23.1.1. Generic Crosspoint IP Features 23.1.2. Generic Crosspoint Performance and Resources
24. Genlock Signal Router Intel® FPGA IP x
24.1. About the Genlock Signal Router IP 24.2. Genlock Signal Router IP Parameters 24.3. Genlock Signal Router IP Interfaces 24.4. Genlock Signal Router IP Registers 24.5. Genlock Signal Router IP Software API
24.1. About the Genlock Signal Router IP x
24.1.1. Genlock Signal Router IP Features 24.1.2. Genlock Signal Router IP Performance and Resources
25. Guard Bands Intel® FPGA IP x
25.1. About the Guard Bands IP 25.2. Guard Bands IP Parameters 25.3. Guard Bands IP Interfaces 25.4. Guard Bands IP Registers 25.5. Guard Bands IP Software API
25.1. About the Guard Bands IP x
25.1.1. Guard Bands IP Performance and Resources
26. Interlacer Intel® FPGA IP x
26.1. About the Interlacer IP 26.2. Interlacer IP Parameters 26.3. Interlacer IP Functional Description 26.4. Interlacer IP Registers 26.5. Interlacer IP Software API
26.1. About the Interlacer IP x
26.1.1. Interlacer IP Performance and Resources
26.3. Interlacer IP Functional Description x
26.3.1. Interlacer IP Interfaces
27. Mixer Intel® FPGA IP x
27.1. About the Mixer IP 27.2. Mixer IP Parameters 27.3. Mixer IP Functional Description 27.4. Mixer IP Registers 27.5. Mixer IP Software API
27.1. About the Mixer IP x
27.1.1. Mixer IP Performance and Resources
27.3. Mixer IP Functional Description x
Alpha blending Alpha blending mode Register map settings Overlay layer enables Restricted offsets Subsampling support Interlaced support Overlay error conditions Packet propagation 27.3.1. Mixer IP Interfaces
28. Pixels in Parallel Converter Intel® FPGA IP x
28.1. About the Pixels in Parallel Converter IP 28.2. Pixels in Parallel Converter IP Parameters 28.3. Pixels in Parallel Converter Interfaces 28.4. Pixels in Parallel Converter Registers 28.5. Pixels in Parallel Converter IP Software API
28.1. About the Pixels in Parallel Converter IP x
28.1.1. Pixels in Parallel Converter IP Performance and Resources
29. Scaler Intel® FPGA IP x
29.1. About the Scaler 29.2. Scaler IP Parameters 29.3. Scaler IP Functional Description 29.4. Scaler IP Registers 29.5. Scaler IP Software API
29.1. About the Scaler x
29.1.1. Scaler IP Performance and Resources
29.2. Scaler IP Parameters x
29.2.1. Scaler Maximum Resolution
29.3. Scaler IP Functional Description x
29.3.1. Coefficient Selection 29.3.2. Coefficient Quantization 29.3.3. Partial Frame Scaling 29.3.4. 422 and 420 Chroma Sampled Data Scaling 29.3.5. Scaler IP Interfaces
29.3.1. Coefficient Selection x
29.3.1.1. Updating Scaler IP Runtime Coefficients
30. Stream Cleaner Intel® FPGA IP x
30.1. About the Stream Cleaner IP 30.2. Stream Cleaner IP Parameters 30.3. Stream Cleaner IP Functional Description
30.1. About the Stream Cleaner IP x
30.1.1. Stream Cleaner IP Performance and Resources
30.3. Stream Cleaner IP Functional Description x
30.3.1. Stream Cleaner IP Interfaces
31. Switch Intel® FPGA IP x
31.1. About the Switch IP 31.2. Switch IP Parameters 31.3. Switch IP Functional Description 31.4. Switch IP Registers 31.5. Switch IP Software API
31.1. About the Switch IP x
31.1.1. Switch IP Performance and Resources
31.3. Switch IP Functional Description x
31.3.1. Switch IP Latency 31.3.2. Switch IP Interfaces
32. Tone Mapping Operator Intel® FPGA IP x
32.1. About the Tone Mapping Operator IP 32.2. TMO IP Parameters 32.3. TMO IP Block Description 32.4. TMO IP Registers 32.5. TMO IP Software API
32.1. About the Tone Mapping Operator IP x
32.1.1. TMO IP Features 32.1.2. TMO IP Performance and Resource Utilization
32.3. TMO IP Block Description x
32.3.1. TMO IP Interfaces 32.3.2. TMO IP Latency
33. Test Pattern Generator Intel® FPGA IP x
33.1. About the Test Pattern Generator IP 33.2. Test Pattern Generator IP Parameters 33.3. Test Pattern Generator IP Functional Description 33.4. Test Pattern Generator IP Registers 33.5. Test Pattern Generator IP Software API
33.1. About the Test Pattern Generator IP x
33.1.1. Test Pattern Generator IP Performance and Resources
33.3. Test Pattern Generator IP Functional Description x
33.3.1. Test Pattern Generator IP Interfaces
34. Video Frame Buffer Intel® FPGA IP x
34.1. About the Video Frame Buffer IP 34.2. Video Frame Buffer IP Parameters 34.3. Video Frame Buffer IP Functional Description 34.4. Video Frame Buffer IP Registers 34.5. Video Frame Buffer IP Software API
34.1. About the Video Frame Buffer IP x
34.1.1. Video Frame Buffer Performance and Resources
34.3. Video Frame Buffer IP Functional Description x
34.3.1. Video Frame Buffer IP Interfaces
35. Video Streaming FIFO Intel® FPGA IP x
35.1. About the Video Streaming FIFO IP 35.2. Video Streaming FIFO IP Parameters 35.3. Video Streaming FIFO IP Interfaces
35.1. About the Video Streaming FIFO IP x
35.1.1. Video Streaming FIFO IP Performance and Resources
36. Video Timing Generator Intel® FPGA IP x
36.1. About the Video Timing Generator IP 36.2. Video Timing Generator IP Parameters 36.3. Video Timing Generator IP Functional Description 36.4. Video Timing Generator IP Interfaces 36.5. Video Timing Generator IP Registers 36.6. Video Timing Generator IP Software API
36.1. About the Video Timing Generator IP x
36.1.1. Video Timing Generator IP Features 36.1.2. Video Timing Generator IP Performance and Resources
37. Warp Intel® FPGA IP x
37.1. About the Warp IP 37.2. Warp IP Parameters 37.3. Warp IP Block Description 37.4. Warp IP Registers 37.5. Warp IP Software API
37.1. About the Warp IP x
37.1.1. Warp IP Features 37.1.2. Warp IP Performance and Resource Utilization
37.3. Warp IP Block Description x
37.3.1. Block Cache Tool 37.3.2. Warp IP Interfaces 37.3.3. Warp IP Latency 37.3.4. External Memory for Warp IP
37.5. Warp IP Software API x
37.5.1. Using Warp IP Software 37.5.2. Warp IP Software Code Examples
38. Design Security x
38.1. Memory Subsystems 38.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Key Intel® FPGA IP
11. Chroma Resampler Intel® FPGA IP
12. Clipper Intel® FPGA IP
13. Clocked Video Input Intel® FPGA IP
14. Clocked Video to Full-Raster Converter Intel® FPGA IP
15. Clocked Video Output Intel® FPGA IP
16. Color Space Converter Intel® FPGA IP
17. Deinterlacer Intel® FPGA IP
18. FIR Filter Intel® FPGA IP
19. Frame Cleaner Intel® FPGA IP
20. Full-Raster to Clocked Video Converter Intel® FPGA IP
21. Full-Raster to Streaming Converter Intel® FPGA IP
22. Genlock Controller Intel® FPGA IP
23. Generic Crosspoint Intel® FPGA IP
24. Genlock Signal Router Intel® FPGA IP
25. Guard Bands Intel® FPGA IP
26. Interlacer Intel® FPGA IP
27. Mixer Intel® FPGA IP
28. Pixels in Parallel Converter Intel® FPGA IP
29. Scaler Intel® FPGA IP
30. Stream Cleaner Intel® FPGA IP
31. Switch Intel® FPGA IP
32. Tone Mapping Operator Intel® FPGA IP
33. Test Pattern Generator Intel® FPGA IP
34. Video Frame Buffer Intel® FPGA IP
35. Video Streaming FIFO Intel® FPGA IP
36. Video Timing Generator Intel® FPGA IP
37. Warp Intel® FPGA IP
38. Design Security
39. Document Revision History for Video and Vision Processing Suite User Guide

27.3. Mixer IP Functional Description

The mixer includes alpha blending for each overlay layer. Alpha blending allows you to vary the transparency of the overlay layer as it is mixed onto the existing image.

Alpha blending

The value to determine the level of transparency is the alpha value. The alpha value varies between 0 and 1. 0 represents full transparency (the overlay layer data does not appear at all). 1 represents fully opaque (the overlay layer completely obscures the existing image).

The IP recursively applies alpha blending, with the image from layer 1 (I 1) blended onto the image from layer 0 (I 0) to create the intermediate image (O 1). The IP then blends the image from layer 2 (I 2) onto 0 1 to create O 2, and so on for each of the layers in turn. For a mixer with N layers, O N-1 is the final output image. The equations show the alpha blending:
Equation 2. Alpha Blending

The IP applies the alpha blending process independently to each color plane in the image and only in the areas where the offset overlay image overlaps the intermediate image.

Alpha blending mode

You can parameterize each layer of the mixer to support different options for how the IP superimposes the foreground layer data onto the existing image. The Alpha blending mode parameter has four options:

  • No blending. The mixer does not include the logic required to perform the alpha blending process for the given layer. The IP overlays the layer image onto the existing image without transparency. It completely replaces the pixel value for the existing image with that of the layer image in the appropriate regions of the output image (as defined by the layer offsets and layer dimensions). You may still select to turn off the overlay at runtime via the register map. No blending does not require any DSP blocks.
  • Alpha from command. The IP includes the logic for alpha blending. The IP takes the alpha value from the register map and applies it as a constant (static alpha) value to every pixel in the layer image. You can still turn off the overlay at runtime via the register map or select to ignore the alpha value entirely and revert to no blending.
  • Alpha from data. The IP includes logic for alpha blending. The incoming video data includes an additional color plane that contains a per-pixel alpha value to determine the transparency. The alpha value is always in the highest index color plane, in the MSBs of each pixel. You can still turn off the overlay at runtime via the register map or select to ignore the alpha value entirely and revert to no blending.
  • Alpha from command or data. You have full flexibility to select at runtime between disabling the overlay, overlay with no blending, overlay with static alpha, or overlay with per pixel alpha.

Register map settings

You can adjust the settings for each overlay layer in the mixer at runtime by making edits to the mixer’s register map through the Avalon memory-mapped control agent interface. When you turn on Lite mode, the properties of the base layer are also set via the register map.

Each overlay layer has five runtime controllable settings when you turn off Lite mode:

  • Layer enable (turns the layer on and off)
  • Layer blend mode
  • Layer static alpha
  • Layer horizontal offset
  • Layer vertical offset

When you turn on Lite mode, two additional registers per overlay layer set the expected resolution for that layer. All these registers are double buffered and edits their values only take effect at the next frame boundary. When you turn off Lite mode, a write is required the COMMIT register for any of the edits to take effect at the next frame boundary.

Overlay layer enables

Each overlay layer n (1 <= n <= 7) has a register in the Avalon memory-mapped control agent register map to define if the IP turns on or off the layer (LAYER n _MODE). The three LSBs of the register value determine how the IP processes the layer.

  • Bit 0. The main enable bit for the given layer. If you set this bit to 0, the IP holds the layer at a field boundary with the tready signal set to 0. When you set this bit to 1, the IP accepts the input packets for the given layer, with one field’s worth of packets accepted for every field on the base layer. The IP propagates the control packets to the output, and either displays the field data as part of the output frame or not, depending on the value in bit 1 of the register.
  • Bit 1. This bit determines if the IP displays the layer or not. If you write 0 to this register, the IP mixes the layer’s field data into the output field (display mode) (according to the settings in the LAYER n _BLEND_MODE register). If you write 1 to this register, the IP does not include the layer’s field data (consume mode). In consume mode, the mixer accepts 1 field of layer data for each field of the base layer. The control packets in the layer stream are still propagated to the output. In display mode, the mixer accepts the layer field data at the input only at times when it must make up part of the output image – according to the vertical and horizontal offsets settings for this layer. In consume mode, the mixer accepts the layer field data as quickly as possible, with no reference to the offsets and no attempt to accept one line of layer field data for each line of base field data.
  • Bit 2. This bit determines how the mixer behaves for the first field after any change to the value in the LAYERn_MODE register. If you set this bit to 0 (and bit 0 is set to 1), the mixer waits for data to be available on layer n before starting the output field. If no data is available, the mixer pauses and waits (hard start condition). If you set this bit to 1, the mixer can progress with the output frame, even if a new frame is not ready at the layer n input. At each field boundary the mixer again checks to see if data becomes available. When data is available at layer n, normal mixing for that layer resumes, and the mixer waits for data on subsequent fields if it is not immediately available (soft-start condition).

Carefully consider the difference between the hard- and soft-start conditions when deciding which is more appropriate for your system.

  • If the layer input comes directly from a source that you cannot stall, such as a clocked video input from HDMI or DisplayPort for example, do no use soft start. In this case the IP forces the output to match the start-of-frame timing of the layer input, as anything else forces a stall on the input. Using soft start allows the output to run in sync with the start-of-frame timing of the base layer (or another overlay layer). If the start-of-frame timing of the overlay layer does not exactly align to that of the base layer, the overlay layer misses the output start of frame and holds off for some amount of time, up to a full frame period in the worst case. This behavior causes the input to overflow.
  • Unless multiple input layers are being externally controlled to force an alignment of their start-of-frame and frame rates, only one layer may come directly from a nonstable source. If the layers are not synchronized at the input, there is no way that each of them can have a hard start without at least one being stalled and overflowing. This typically means that, at most, only one layer should use the hard start condition.
  • Typically, a source that you can stall drives most layers – such as a frame buffer with drop or repeat of frames. You can stall a frame buffer without overflowing. A soft start condition is more appropriate, as it allows any existing output from the mixer to retain its current start-of-frame timing. The overlay layer from the frame buffer synchronizes to the existing timing. Because the output timing stays the same, no glitch in any display connected to it occurs.

The mixer does not commit to processing a field until the data for all layers is pending at each input. Until the IP reaches this condition, the mixer remains in a state where you can still edit the register map via the Avalon memory-mapped control agent interface. The changes take effect immediately because the mixer is between fields. If the system experiences a loss of video on any input, the system controller can turn off the given layer and avoid lock-up in the system.

Restricted offsets

You supply a horizontal offset for each overlay layer. This determines the pixel index within the line at which that layer begins to be mixed onto the background. If the number of pixels in parallel is 1, it is trivial to begin mixing at any pixel offset. If the number of pixels in parallel is greater than 1, any offset that is not an integer multiple of pixels in parallel gives additional challenges.

The mixer must include logic to shift pixels within and across data words by any number of pixels between 0 and the number of pixels in parallel minus 1. If the number of pixels in parallel is small, the ALM cost of this extra hardware is relatively small, but at 4 to 8 pixels in parallel the resource usage can be a significant proportion of the overall mixer ALM count.

If you limit the horizontal offset for any layer such that it is always an integer multiple of the pixels in parallel, you can turn on use restricted offsets for that layer. Then the mixer omits the extra pixel shifting logic for that layer and reduces the ALM cost. If you turn on use restricted offsets for any layer and you try to set a horizontal offset for that layer to a noninteger multiple of pixels in parallel, the internal logic moves the offset back to the nearest integer position.

Subsampling support

The mixer supports 4:4:4, 4:2:2 and 4:2:0 chroma sampled video data and can switch dynamically between chroma samplings at runtime. Full variants drive the current chroma sampling by the image information packet that accompanies each field. Lite variants let you set the chroma sampling via the register map. The following restrictions regarding chroma sampling apply:

  • All layers must be the same chroma sampling as the base layer (layer 0).
  • For 4:2:2 chroma sampling, the field width for all layers (including the base layer) must be an integer multiple of 2.
  • For 4:2:2 chroma sampling, the horizontal offset for each active overlay layer must be an integer multiple of 2.
  • For 4:2:0 chroma sampling, both the field height and field width for all layers (including the base layer) must be integer multiples of 2.
  • For 4:2:0 chroma sampling, both the horizontal and vertical offsets for each active layer must be integer multiples of 2.

Interlaced support

The mixer is mainly for progressive video but does have limited support for interlaced video for full variants. You should apply vertical offsets within each field and not within the progressive frame. Each layer should supply either an F0 or F1 field in sync with the base layer (layer 0). If any layer that you turn on for display provides an F1 field when the base layer provides F0, or vice versa, the IP asserts the broken-field flag in the output end of frame packet.

Overlay error conditions

Each overlay layer has an expected field width and height, derived either from the image information packets for full variants, or the register map for lite variants. Each layer also has a horizontal and vertical offset within the base layer which you specify through the register map. If the sum of the overlay field width and the horizontal offset for any layer exceed the field width of the base layer, the IP does not display layer (the IP forces the layer into consume mode). The IP asserts the broken-field flag in the output end of frame packet

Packet propagation

In the full variant of Intel FPGA streaming video, the input stream on each layer may contain image information, end of field, and auxiliary control packets with the video line packets. The mixer adheres to the following rules when handling these packets from each layer:

  • Image information and end of frame packets. The image information and end of frame packet from the base layer (layer 0) propagate to the output. The image information packet is always unaltered. The end of frame packet propagates with the broken-field flag potentially edited, but otherwise unaltered. If the IP asserts the broken-field flag in the base layer or any displayed overlay layer. Then the IP asserts the output broken field flag. The broken-field flag in the end of frame packet may also be asserted if the mixer experiences an error during processing, such as an interlaced field mismatch.
  • Auxiliary control packets. When any layer is active, either for display or consume, its auxiliary control packets propagate to the output with the video packets from the base layer. The IP takes the auxiliary control packets from each layer in sequence, both before and after the field line packets.
Figure 61. Control packet propagationThe figure assumes n layers and all n layers are active on the current field:

Section Content
Mixer IP Interfaces

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