Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 12/12/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Genlock Controller Intel® FPGA IP 23. Generic Crosspoint Intel® FPGA IP 24. Genlock Signal Router Intel® FPGA IP 25. Guard Bands Intel® FPGA IP 26. Interlacer Intel® FPGA IP 27. Mixer Intel® FPGA IP 28. Pixels in Parallel Converter Intel® FPGA IP 29. Scaler Intel® FPGA IP 30. Stream Cleaner Intel® FPGA IP 31. Switch Intel® FPGA IP 32. Tone Mapping Operator Intel® FPGA IP 33. Test Pattern Generator Intel® FPGA IP 34. Video Frame Buffer Intel® FPGA IP 35. Video Streaming FIFO Intel® FPGA IP 36. Video Timing Generator Intel® FPGA IP 37. Warp Intel® FPGA IP 38. Design Security 39. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. AXI-Stream Broadcaster Intel® FPGA IP x
9.1. About the AXI-Stream Broadcaster IP 9.2. AXI-Stream Broadcaster IP Parameters 9.3. AXI-Stream Broadcaster IP Interfaces
9.1. About the AXI-Stream Broadcaster IP x
9.1.1. AXI-Stream Broadcaster IP Features 9.1.2. AXI-Stream Broadcaster IP Performance and Resources
10. Chroma Key Intel® FPGA IP x
10.1. About the Chroma Key IP 10.2. Chroma Key IP Parameters 10.3. Chroma Key IP Interfaces 10.4. Chroma Key Replacement 10.5. Chroma Key IP Registers 10.6. Chroma Key IP Software API
10.1. About the Chroma Key IP x
10.1.1. Chroma Key IP Performance and Resources
11. Chroma Resampler Intel® FPGA IP x
11.1. About the Chroma Resampler IP 11.2. Chroma Resampler IP Parameters 11.3. Chroma Resampler IP Functional Description 11.4. Chroma Resampler IP Registers 11.5. Chroma Resampler IP Software API
11.1. About the Chroma Resampler IP x
11.1.1. Chroma Resampler Performance and Resources
11.3. Chroma Resampler IP Functional Description x
11.3.1. Chroma Resampler IP Interfaces
12. Clipper Intel® FPGA IP x
12.1. About the Clipper IP 12.2. Clipper IP Parameters 12.3. Clipper IP Interfaces 12.4. Clipper IP Registers 12.5. Clipper IP Software API
12.1. About the Clipper IP x
12.1.1. Clipper IP Performance and Resources
13. Clocked Video Input Intel® FPGA IP x
13.1. About the Clocked Video Input IP 13.2. Initializing the Clocked Video Input IP 13.3. Clocked Video Input IP Parameters 13.4. Clocked Video Input IP Interfaces 13.5. Clocked Video Input IP Registers 13.6. Clocked Video Input IP Software API
13.1. About the Clocked Video Input IP x
13.1.1. Clocked Video Input IP Features 13.1.2. Clocked Video Input IP Performance and Resources
14. Clocked Video to Full-Raster Converter Intel® FPGA IP x
14.1. About the Clocked Video to Full-Raster Converter IP 14.2. Clocked Video to Full-Raster Converter Parameters 14.3. Clocked Video to Full-Raster Converter Block Description 14.4. Clocked Video Converter to Full-Raster IP Registers
14.1. About the Clocked Video to Full-Raster Converter IP x
14.1.1. Clocked Video to Full-Raster Converter Features 14.1.2. Clocked Video to Full-Raster Converter Performance and Resources
14.3. Clocked Video to Full-Raster Converter Block Description x
14.3.1. Clocked Video to Full-Raster Converter Interfaces
15. Clocked Video Output Intel® FPGA IP x
15.1. About the Clocked Video Output IP 15.2. Clocked Video Output IP Parameters 15.3. Clocked Video Output IP Functional Description 15.4. Clocked Video Output IP Interfaces 15.5. Clocked Video Output IP Registers 15.6. Clocked Video Output IP Software API
15.1. About the Clocked Video Output IP x
15.1.1. Clocked Video Output IP Performance and Resources 15.1.2. Clocked Video Output IP Features
16. Color Space Converter Intel® FPGA IP x
16.1. About the Color Space Converter IP 16.2. Color Space Converter IP Parameters 16.3. Color Space Converter IP Functional Description 16.4. Color Space Converter IP Registers 16.5. Color Space Converter IP Software API
16.1. About the Color Space Converter IP x
16.1.1. Color Space Converter IP Features 16.1.2. Color Space Converter IP Performance and Resources
16.3. Color Space Converter IP Functional Description x
16.3.1. Color Space Converter IP Interfaces
17. Deinterlacer Intel® FPGA IP x
17.1. About the Deinterlacer IP 17.2. Deinterlacer Parameters 17.3. Deinterlacer Interfaces 17.4. Deinterlacer Registers 17.5. Deinterlacer IP Software API
17.1. About the Deinterlacer IP x
17.1.1. Deinterlacer Performance and Resources
18. FIR Filter Intel® FPGA IP x
18.1. About the FIR Filter 18.2. FIR Filter Parameters 18.3. FIR Filter IP Operation 18.4. FIR Filter Interfaces 18.5. FIR Filter Registers 18.6. FIR Filter IP Software API
18.1. About the FIR Filter x
18.1.1. FIR Filter IP Performance and Resources
18.3. FIR Filter IP Operation x
18.3.1. FIR Filter Processing 18.3.2. FIR Filter Precision 18.3.3. FIR Coefficient Specification 18.3.4. FIR Filter Symmetry 18.3.5. Result to Output Data Type Conversion
18.3.4. FIR Filter Symmetry x
18.3.4.1. No Symmetry 18.3.4.2. Horizontal Symmetry 18.3.4.3. Vertical Symmetry 18.3.4.4. Horizontal and Vertical Symmetry 18.3.4.5. Diagonal Symmetry
19. Frame Cleaner Intel® FPGA IP x
19.1. About the Frame Cleaner IP 19.2. Frame Cleaner IP Parameters 19.3. Frame Cleaner IP Functional Description 19.4. Frame Cleaner IP Interfaces 19.5. Frame Cleaner IP Registers 19.6. Frame Cleaner IP Software API
19.1. About the Frame Cleaner IP x
19.1.1. Frame Cleaner IP Performance and Resources
20. Full-Raster to Clocked Video Converter Intel® FPGA IP x
20.1. About the Full-Raster to Clocked Video Converter 20.2. Full Raster to Clocked Video Converter Parameters 20.3. Full-Raster to Clocked Video Converter Block Description 20.4. Full-Raster to Clocked Video Converter Registers
20.1. About the Full-Raster to Clocked Video Converter x
20.1.1. Full-Raster to Clocked Video Converter Features 20.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
20.3. Full-Raster to Clocked Video Converter Block Description x
20.3.1. Full Raster to Clocked Video Converter Interfaces
21. Full-Raster to Streaming Converter Intel® FPGA IP x
21.1. About the Full-Raster to Streaming Converter IP 21.2. Full-Raster to Streaming Converter Parameters 21.3. Full-Raster to Streaming Converter Block Description
21.1. About the Full-Raster to Streaming Converter IP x
21.1.1. Full-Raster to Streaming Converter Features 21.1.2. Full-Raster to Streaming Converter Performance and Resources
21.3. Full-Raster to Streaming Converter Block Description x
21.3.1. Full-Raster to Streaming Converter Interfaces
22. Genlock Controller Intel® FPGA IP x
22.1. About the Genlock Controller IP 22.2. Genlock Controller IP Parameters 22.3. Genlock Controller IP Functional Description 22.4. Using Genlock Controller IP Software 22.5. Genlock Controller IP Registers 22.6. Genlock Controller IP Software API
22.1. About the Genlock Controller IP x
22.1.1. Genlock Controller IP Performance and Resources
22.3. Genlock Controller IP Functional Description x
22.3.1. Genlock Controller IP Interfaces
22.4. Using Genlock Controller IP Software x
22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 22.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 22.4.3. Setting the VCXO hold over 22.4.4. Restarting the Genlock Controller IP 22.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 22.4.7. Disturbing a Reference Clock (a cable pull)
23. Generic Crosspoint Intel® FPGA IP x
23.1. About the Generic Crosspoint IP 23.2. Generic Crosspoint IP Parameters 23.3. Generic Crosspoint IP Interfaces 23.4. Generic Crosspoint IP Registers 23.5. Generic Crosspoint IP Software API
23.1. About the Generic Crosspoint IP x
23.1.1. Generic Crosspoint IP Features 23.1.2. Generic Crosspoint Performance and Resources
24. Genlock Signal Router Intel® FPGA IP x
24.1. About the Genlock Signal Router IP 24.2. Genlock Signal Router IP Parameters 24.3. Genlock Signal Router IP Interfaces 24.4. Genlock Signal Router IP Registers 24.5. Genlock Signal Router IP Software API
24.1. About the Genlock Signal Router IP x
24.1.1. Genlock Signal Router IP Features 24.1.2. Genlock Signal Router IP Performance and Resources
25. Guard Bands Intel® FPGA IP x
25.1. About the Guard Bands IP 25.2. Guard Bands IP Parameters 25.3. Guard Bands IP Interfaces 25.4. Guard Bands IP Registers 25.5. Guard Bands IP Software API
25.1. About the Guard Bands IP x
25.1.1. Guard Bands IP Performance and Resources
26. Interlacer Intel® FPGA IP x
26.1. About the Interlacer IP 26.2. Interlacer IP Parameters 26.3. Interlacer IP Functional Description 26.4. Interlacer IP Registers 26.5. Interlacer IP Software API
26.1. About the Interlacer IP x
26.1.1. Interlacer IP Performance and Resources
26.3. Interlacer IP Functional Description x
26.3.1. Interlacer IP Interfaces
27. Mixer Intel® FPGA IP x
27.1. About the Mixer IP 27.2. Mixer IP Parameters 27.3. Mixer IP Functional Description 27.4. Mixer IP Registers 27.5. Mixer IP Software API
27.1. About the Mixer IP x
27.1.1. Mixer IP Performance and Resources
27.3. Mixer IP Functional Description x
27.3.1. Mixer IP Interfaces
28. Pixels in Parallel Converter Intel® FPGA IP x
28.1. About the Pixels in Parallel Converter IP 28.2. Pixels in Parallel Converter IP Parameters 28.3. Pixels in Parallel Converter Interfaces 28.4. Pixels in Parallel Converter Registers 28.5. Pixels in Parallel Converter IP Software API
28.1. About the Pixels in Parallel Converter IP x
28.1.1. Pixels in Parallel Converter IP Performance and Resources
29. Scaler Intel® FPGA IP x
29.1. About the Scaler 29.2. Scaler IP Parameters 29.3. Scaler IP Functional Description 29.4. Scaler IP Registers 29.5. Scaler IP Software API
29.1. About the Scaler x
29.1.1. Scaler IP Performance and Resources
29.2. Scaler IP Parameters x
29.2.1. Scaler Maximum Resolution
29.3. Scaler IP Functional Description x
29.3.1. Coefficient Selection 29.3.2. Coefficient Quantization 29.3.3. Partial Frame Scaling 29.3.4. 422 and 420 Chroma Sampled Data Scaling 29.3.5. Scaler IP Interfaces
29.3.1. Coefficient Selection x
29.3.1.1. Updating Scaler IP Runtime Coefficients
30. Stream Cleaner Intel® FPGA IP x
30.1. About the Stream Cleaner IP 30.2. Stream Cleaner IP Parameters 30.3. Stream Cleaner IP Functional Description
30.1. About the Stream Cleaner IP x
30.1.1. Stream Cleaner IP Performance and Resources
30.3. Stream Cleaner IP Functional Description x
30.3.1. Stream Cleaner IP Interfaces
31. Switch Intel® FPGA IP x
31.1. About the Switch IP 31.2. Switch IP Parameters 31.3. Switch IP Functional Description 31.4. Switch IP Registers 31.5. Switch IP Software API
31.1. About the Switch IP x
31.1.1. Switch IP Performance and Resources
31.3. Switch IP Functional Description x
31.3.1. Switch IP Latency 31.3.2. Switch IP Interfaces
32. Tone Mapping Operator Intel® FPGA IP x
32.1. About the Tone Mapping Operator IP 32.2. TMO IP Parameters 32.3. TMO IP Block Description 32.4. TMO IP Registers 32.5. TMO IP Software API
32.1. About the Tone Mapping Operator IP x
32.1.1. TMO IP Features 32.1.2. TMO IP Performance and Resource Utilization
32.3. TMO IP Block Description x
32.3.1. TMO IP Interfaces 32.3.2. TMO IP Latency
33. Test Pattern Generator Intel® FPGA IP x
33.1. About the Test Pattern Generator IP 33.2. Test Pattern Generator IP Parameters 33.3. Test Pattern Generator IP Functional Description 33.4. Test Pattern Generator IP Registers 33.5. Test Pattern Generator IP Software API
33.1. About the Test Pattern Generator IP x
33.1.1. Test Pattern Generator IP Performance and Resources
33.3. Test Pattern Generator IP Functional Description x
33.3.1. Test Pattern Generator IP Interfaces
34. Video Frame Buffer Intel® FPGA IP x
34.1. About the Video Frame Buffer IP 34.2. Video Frame Buffer IP Parameters 34.3. Video Frame Buffer IP Functional Description 34.4. Video Frame Buffer IP Registers 34.5. Video Frame Buffer IP Software API
34.1. About the Video Frame Buffer IP x
34.1.1. Video Frame Buffer Performance and Resources
34.3. Video Frame Buffer IP Functional Description x
34.3.1. Video Frame Buffer IP Interfaces
35. Video Streaming FIFO Intel® FPGA IP x
35.1. About the Video Streaming FIFO IP 35.2. Video Streaming FIFO IP Parameters 35.3. Video Streaming FIFO IP Interfaces
35.1. About the Video Streaming FIFO IP x
35.1.1. Video Streaming FIFO IP Performance and Resources
36. Video Timing Generator Intel® FPGA IP x
36.1. About the Video Timing Generator IP 36.2. Video Timing Generator IP Parameters 36.3. Video Timing Generator IP Functional Description 36.4. Video Timing Generator IP Interfaces 36.5. Video Timing Generator IP Registers 36.6. Video Timing Generator IP Software API
36.1. About the Video Timing Generator IP x
36.1.1. Video Timing Generator IP Features 36.1.2. Video Timing Generator IP Performance and Resources
37. Warp Intel® FPGA IP x
37.1. About the Warp IP 37.2. Warp IP Parameters 37.3. Warp IP Block Description 37.4. Warp IP Registers 37.5. Warp IP Software API
37.1. About the Warp IP x
37.1.1. Warp IP Features 37.1.2. Warp IP Performance and Resource Utilization
37.3. Warp IP Block Description x
37.3.1. Block Cache Tool 37.3.2. Warp IP Interfaces 37.3.3. Warp IP Latency 37.3.4. External Memory for Warp IP
37.5. Warp IP Software API x
37.5.1. Using Warp IP Software 37.5.2. Warp IP Software Code Examples
38. Design Security x
38.1. Memory Subsystems 38.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Key Intel® FPGA IP
11. Chroma Resampler Intel® FPGA IP
12. Clipper Intel® FPGA IP
13. Clocked Video Input Intel® FPGA IP
14. Clocked Video to Full-Raster Converter Intel® FPGA IP
15. Clocked Video Output Intel® FPGA IP
16. Color Space Converter Intel® FPGA IP
17. Deinterlacer Intel® FPGA IP
18. FIR Filter Intel® FPGA IP
19. Frame Cleaner Intel® FPGA IP
20. Full-Raster to Clocked Video Converter Intel® FPGA IP
21. Full-Raster to Streaming Converter Intel® FPGA IP
22. Genlock Controller Intel® FPGA IP
23. Generic Crosspoint Intel® FPGA IP
24. Genlock Signal Router Intel® FPGA IP
25. Guard Bands Intel® FPGA IP
26. Interlacer Intel® FPGA IP
27. Mixer Intel® FPGA IP
28. Pixels in Parallel Converter Intel® FPGA IP
29. Scaler Intel® FPGA IP
30. Stream Cleaner Intel® FPGA IP
31. Switch Intel® FPGA IP
32. Tone Mapping Operator Intel® FPGA IP
33. Test Pattern Generator Intel® FPGA IP
34. Video Frame Buffer Intel® FPGA IP
35. Video Streaming FIFO Intel® FPGA IP
36. Video Timing Generator Intel® FPGA IP
37. Warp Intel® FPGA IP
38. Design Security
39. Document Revision History for Video and Vision Processing Suite User Guide

32.5. TMO IP Software API

The IP includes a software driver that configures and controls all the IP parameters.

Software Driver Example 

int main()
{
  int ret = -1;

  /* Initialize datapath Video Timing Generator instance
  /* This API function is not part of the TMO driver. */ 
  /* Hence, it is up to the user to implement it, to provide VIDEO_WIDTH, VIDEO_HEIGHT values */
  datapath_vtiming_config(VTIMING_TMO_BASE, 1);

  /* Initialize TMO IP instance*/
  intel_vvp_base_t base = INTEL_VVP_TMO_BASE;
  intel_vvp_tmo_instance_t intel_vvp_tmo_instance;

  /*Query TMO IP instance, to know whether is has been initialized correctly. */
  /* A value == '0' indicates TMO IP has been initialized correctly  */
  ret = intel_vvp_tmo_init_instance(&intel_vvp_tmo_instance, base);

  if (ret == 0)
  {
    /* TMO IP Bypass control */
    uint32_t bypass = 0;

    intel_vvp_tmo_set_bypass(&intel_vvp_tmo_instance, bypass);
    printf("Intel VVP TMO Bypass %s\n\n", bypass ? "ENABLED" : "DISABLED");

    /* Initialize TMO IP to specific video resolution */
    intel_vvp_tmo_set_resolution(&intel_vvp_tmo_instance, VIDEO_WIDTH, VIDEO_HEIGHT);

    /* Update TMO IP volume control values */
    intel_vvp_tmo_set_volume(&intel_vvp_tmo_instance, VOLUME_CTL_USER);
    intel_vvp_tmo_set_threshold(&intel_vvp_tmo_instance, INT_THR_USER);

    printf("TMO initialization done\n");
    fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK);

    while (1)
    {
      /* This function checks if TMO IP bypass mode and/or volume control values need to be updated */
      /* but it is not part of the TMO IP SW driver package. Hence, customers are expected */
      /* to implement their own function according to their specific needs */   
      process_user_input(&intel_vvp_tmo_instance);

      /* This part of the code is for debug purpose only */
      /* Two conditions are checked: */
            
      /* Condition #1: Missing data collection per tile */
      static const uint32_t num_rows = 4;
      static const uint32_t row_mask = ~(~0u << num_rows);

    





      /* Read TMO IP debug register to check for error conditions */
      uint32_t reg_val = intel_vvp_tmo_get_debug(&intel_vvp_tmo_instance;

      if (reg_val & row_mask)
      {
        printf ("Timeout rows: ";

        for (uint32_t i = 0; i < num_rows; ++ i)
        {
          if (reg_val & (0x1 << i))
            printf("%"PRIu32" ", i);
        }

        printf("\n";
      }

      /* Condition #2: Missing entire video frame */
      if (reg_val & 0x100)
      {
        printf ("FSYNC toggle error\n";
      }

      /* Set TMO IP debug register to capture new error conditions */
      intel_vvp_tmo_set_debug(&intel_vvp_tmo_instance, reg_val);
    }
  }
  else
  {
    printf("Error initializing intel_vvp_tmo instance: %d\n", ret);
  }

  return ret;
}

The TMO IP software driver does not include the process_user_input(&intel_vvp_tmo_instance) function, as its implementation depends on your system requirements and specifications. You can query and update TMO strength volume values in various ways. For example, you can implement the process_user_input(&intel_vvp_tmo_instance) in this way: 

void process_user_input(intel_vvp_tmo_instance* instance)
{
  int c = getchar();
  static const int32_t VOL_STEP = 5;
  static const int32_t TS_STEP = 1000;
  int vol_delta = 0;
  int ts_delta = 0;

  if(c != EOF)
  {
    switch(c)
    {
      case 'w':
      case 'W':
        vol_delta = VOL_STEP;
        break;
      case 's':
      case 'S':
        vol_delta = -VOL_STEP;
        break;
      case 'd':
      case 'D':
        ts_delta = TS_STEP;
        break;
      case 'a':
      case 'A':
        ts_delta = - TS_STEP;
        break;
      case 'b':
      case 'B':
      {
        uint32_t bypass = intel_vvp_tmo_get_bypass(instance);
        bypass ^= 0x1;
        intel_vvp_tmo_set_bypass(instance, bypass);
        printf("TMO Bypass %s\n\n", bypass ? "ENABLED" : "DISABLED");
      }
        break;
      default:
        break;
    }

    if(vol_delta || ts_delta)
    {
      int32_t vol = (int32_t)(intel_vvp_tmo_get_volume(instance));
      int32_t ts = (int32_t)(intel_vvp_tmo_get_threshold(instance));

      vol += vol_delta;
      ts += ts_delta;

      if(vol > 100)
      vol = 100;

      if(vol < 0)
      vol = 0;

      if(ts > 9000)
      ts = 9000;

      if(ts < 0)
      ts = 0;

      printf("VOL: %"PRIi32"\n", vol);
      printf("TS: %"PRIi32"\n", ts);

      intel_vvp_tmo_set_volume(instance, (uint32_t)(vol));
      intel_vvp_tmo_set_threshold(instance, (uint32_t)(ts));
    }
  }
}

All the API functions require a pointer to intel_vvp_tmo_instance_t structure as the first parameter. The structure represents an individual instance of TMO IP and defined as following: 

typedef struct intel_vvp_tmo_instance {
intel_vvp_tmo_base_t base;
} intel_vvp_tmo_instance_t;

Where:

intel_vvp_tmo_base_t base is a platform specific access handler that the driver uses to access configuration and control registers of the IP. Default definition for a bare metal environment is 32-bit unsigned integer representing base address of the TMO IP on the external CPU bus.

The internal driver uses the following macros to access individual registers of the IP:

  • tmoss_read_reg(x) – read register
  • tmoss_write_reg(x,y) – write register

Where:

x is the byte offset of the register from the IP core base address

y is the 32-bit register value to write.

Default bare metal implementation of the IP register access provided in the file intel_vvp_tmo_io.h. Provide alternative implementations through separate header files included conditionally from intel_vvp_tmo_io.h.

Byte offsets of all TMO IP registers are defined in the file intel_vvp_tmo_regs.h.

Table 551.   Software driver API reference The software driver for TMO IP provides various API functions
Name Description
intel_vvp_tmo_init_instance Initialize TMO IP driver instance
intel_vvp_tmo_set_bypass Set TMO IP into bypass mode
intel_vvp_tmo_get_bypass Return current setting of the bypass mode
intel_vvp_tmo_set_resolution Set input video resolution for TMO IP
intel_vvp_tmo_set_volume Adjust fine-level TMO volume as a percentage, which allows more granularity when setting TMO strength value
intel_vvp_tmo_get_volume Return current level of TMO strength
intel_vvp_tmo_set_threshold Adjust coarse level TMO volume, which allows setting TMO strength value
intel_vvp_tmo_get_threshold Return current value of fine-level TMO volume adjustment
intel_vvp_tmo_set_roi_en Enable or disable the region of interest mode
intel_vvp_tmo_set_roi_swap Enable or disable swap region in region of interest mode
intel_vvp_tmo_set_roi_horizontal_x0x1 Set horizontal starting and ending positions of the region of interest, implicitly enables region of interest mode
intel_vvp_tmo_set_roi_vertical_y0y1 Set vertical starting and ending positions of the region of interest, implicitly enables region of interest mode
intel_vvp_tmo_get_roi_en Return current value of the region of interest enable bit
intel_vvp_tmo_get_roi_swap Return current value of the region of interest swap bit
intel_vvp_tmo_get_roi_horizontal_x0 Return current value of the horizontal starting position of the region of interest
intel_vvp_tmo_get_roi_horizontal_x1 Return current value of the horizontal ending position of the region of interest
intel_vvp_tmo_get_roi_vertical_y0 Return current value of the vertical starting position of the region of interest
intel_vvp_tmo_get_roi_vertical_y1 Return current value of the vertical ending position of the region of interest
intel_vvp_tmo_get_pip Return current configuration value of the number of pixels-in-parallel
intel_vvp_tmo_get_resolution_width Return width of the current video resolution in number of pixels
intel_vvp_tmo_get_resolution_height Return height of the current video resolution in number of lines
intel_vvp_tmo_get_debug Return current value of debug information register
intel_vvp_tmo_set_debug Clear individual bits in debug information register

intel_vvp_tmo_init_instance

int intel_vvp_tmo_init_instance(intel_vvp_tmo_instance_t* instance, intel_vvp_tmo_base_t base)
Description
Initialize TMO software driver instance
Arguments
instance – pointer to the TMO software driver instance structure
base – platform specific IP access handle. In a bare metal environment this is typically defined as 32-bit unsigned integer representing base address of the IP on the external CPU bus
Return Value
Zero on success, negative integer otherwise

intel_vvp_tmo_set_bypass

void intel_vvp_tmo_set_bypass(intel_vvp_tmo_instance_t* instance, uint32_t bypass)
Description
Enable/disable TMO bypass mode. With bypass mode the TMO IP does not process the incoming video stream and passes it as is.
Arguments
instance – pointer to the TMO software driver instance structure
bypass - 1 – enable bypass mode; 0 – disable bypass mode
Return Value
void

intel_vvp_tmo_get_bypass

uint32_t intel_vvp_tmo_get_bypass(intel_vvp_tmo_instance_t* instance)
Description
Get the current setting of the bypass mode
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
1 – bypass mode is enabled; 0 – bypass mode is disabled

intel_vvp_tmo_set_resolution

void intel_vvp_tmo_set_resolution(intel_vvp_tmo_instance_t* instance, const uint32_t width, const uint32_t height)
Description
Set up TMO IP for the required video resolution
Arguments
instance – pointer to the TMO software driver instance structure
width - video width in pixels e.g. 1920
height - video height in lines e.g. 1080
Return Value
void

intel_vvp_tmo_set_volume

void intel_vvp_tmo_set_volume(intel_vvp_tmo_instance_t* instance, const uint32_t volume)
Description
Set desired tone enhancement strength
Arguments
instance – pointer to the TMO software driver instance structure
volume - tone enhancement strength in the range [0..100]
Return Value
void

intel_vvp_tmo_get_volume

uint32_t intel_vvp_tmo_get_volume(intel_vvp_tmo_instance_t* instance)
Description
Get currently configured tone enhancement strength
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Current tone enhancement strength in the range [0..100]

intel_vvp_tmo_set_threshold

void intel_vvp_tmo_set_threshold(intel_vvp_tmo_instance_t* instance, const uint32_t threshold)
Description
Set fine-level tone enhancement strength
Arguments
instance – pointer to the TMO software driver instance structure
threshold – fine level tone enhancement strength in the range [0..10000]
Return Value
void

intel_vvp_tmo_get_threshold

uint32_t intel_vvp_tmo_get_threshold(intel_vvp_tmo_instance_t* instance)
Description
Get currently configured fine-level tone enhancement strength
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Current fine level tone enhancement strength in the range [0..10000]

intel_vvp_tmo_set_roi_en

void intel_vvp_tmo_set_roi_en(intel_vvp_tmo_instance_t* instance, uint32_t roi_en)
Description
Enable or disable the region of interest mode
Arguments

instance – pointer to the TMO software driver instance

region of interest enable – 1 – enable region of interest mode, 0 – disable region of interest mode

Return Value
void

intel_vvp_tmo_set_roi_swap

void intel_vvp_tmo_set_roi_swap(intel_vvp_tmo_instance_t* instance, uint32_t roi_swap)
Description
Enable or disable swap region in region of interest mode
Arguments

instance – pointer to the TMO software driver instance

region of interest swap – 1 – swap the region of interest, 0 – do not swap the region of interest

Return Value
void

intel_vvp_tmo_set_roi_horizontal_x0x1 

void intel_vvp_tmo_set_roi_horizontal_x0x1(intel_vvp_tmo_instance_t* instance, const uint32_t
          pos_x0, const uint32_t pos_x1)
Description
Set horizontal starting and ending positions of the region of interest, implicitly enables region of interest mode
Arguments

instance – pointer to the TMO software driver instance

horizontal region of interest starting position – starting pixel position of the region of interest in the width dimension, divided by pixels-in-parallel

horizontal region of interest ending position – ending pixel position of the region of interest in the width dimension, divided by pixels-in-parallel

Return Value
void

intel_vvp_tmo_set_roi_vertical_y0y1 

void intel_vvp_tmo_set_roi_vertical_y0y1(intel_vvp_tmo_instance_t* instance, const uint32_t
          pos_y0, const uint32_t pos_y1)
Description
Set vertical starting and ending positions of the region of interest, implicitly enables region of interest mode
Arguments

instance – pointer to the TMO software driver instance

vertical region of interest starting position – starting line position of the region of interest in the height dimension

vertical region of interest ending position – ending line position of the region of interest in the height dimension

Return Value
void

intel_vvp_tmo_get_roi_en 

uint32_t
intel_vvp_tmo_get_roi_en(intel_vvp_tmo_instance_t* instance)
Description
Return current value of the region of interest enable bit
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
1 – region of interest mode is enabled; 0 – region of interest mode is disabled

intel_vvp_tmo_get_roi_swap 

uint32_t
intel_vvp_tmo_get_roi_swap(intel_vvp_tmo_instance_t* instance)
Description
Return current value of the region of interest swap bit
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
1 – region of interest is swapped; 0 – region of interest is not swapped

intel_vvp_tmo_get_roi_horizontal_x0 

uint32_t
intel_vvp_tmo_get_roi_horizontal_x0(intel_vvp_tmo_instance_t*
instance)
Description
Return current value of the horizontal starting position of the region of interest
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Current value of the horizontal starting pixel position of the region of interest, divided by pixels-in-parallel

intel_vvp_tmo_get_roi_horizontal_x1 

uint32_t
intel_vvp_tmo_get_roi_horizontal_x1(intel_vvp_tmo_instance_t*
instance)
Description
Return current value of the horizontal ending position of the region of interest
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Current value of the horizontal ending pixel position of the region of interest, divided by pixels-in-parallel

intel_vvp_tmo_get_roi_vertical_y0 

uint32_t
intel_vvp_tmo_get_roi_vertical_y0(intel_vvp_tmo_instance_t*
instance)
Description
Return current value of the vertical starting position of the region of interest
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Current value of the vertical starting line position of the region of interest

intel_vvp_tmo_get_roi_vertical_y1 

uint32_t
intel_vvp_tmo_get_roi_vertical_y1(intel_vvp_tmo_instance_t*
instance)
Description
Return current value of the vertical ending position of the region of interest
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Current value of the vertical ending line position of the region of interest

intel_vvp_tmo_get_pip 

uint32_t
intel_vvp_tmo_get_pip(intel_vvp_tmo_instance_t*
instance)
Description
Return current configuration value of the number of pixels-in-parallel
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Configuration value of the number of pixels-in-parallel

intel_vvp_tmo_get_resolution_width 

uint32_t
intel_vvp_tmo_get_resolution_width(intel_vvp_tmo_instance_t*
instance)
Description
Return width of the current video resolution in number of pixels
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Current value of the video resolution width in number of pixels

intel_vvp_tmo_get_resolution_height 

uint32_t
intel_vvp_tmo_get_resolution_height(intel_vvp_tmo_instance_t*
instance)
Description
Return height of the current video resolution in number of lines
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Current value of the video resolution height in number of lines

intel_vvp_tmo_get_debug

uint32_t intel_vvp_tmo_get_debug(intel_vvp_tmo_instance_t* instance)
Description
Get current value of the Debug information register Ext_Reg_0xA0
Arguments
instance – pointer to the TMO software driver instance structure
Return Value
Current value of Ext_Reg_0xA0 as 32-bit unsigned integer

intel_vvp_tmo_set_debug

void intel_vvp_tmo_set_debug(intel_vvp_tmo_instance_t* instance, uint32_t val)
Description
Clear individual bits of the Debug information register Ext_Reg_0xA0
Arguments
instance – pointer to the TMO software driver instance structure
val - bit mask of the bits within the debug register to clear
Return Value
void
Related Information
Level Two Title