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1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. AXI-Stream Broadcaster Intel® FPGA IP
10. Chroma Key Intel® FPGA IP
11. Chroma Resampler Intel® FPGA IP
12. Clipper Intel® FPGA IP
13. Clocked Video Input Intel® FPGA IP
14. Clocked Video to Full-Raster Converter Intel® FPGA IP
15. Clocked Video Output Intel® FPGA IP
16. Color Space Converter Intel® FPGA IP
17. Deinterlacer Intel® FPGA IP
18. FIR Filter Intel® FPGA IP
19. Frame Cleaner Intel® FPGA IP
20. Full-Raster to Clocked Video Converter Intel® FPGA IP
21. Full-Raster to Streaming Converter Intel® FPGA IP
22. Genlock Controller Intel® FPGA IP
23. Generic Crosspoint Intel® FPGA IP
24. Genlock Signal Router Intel® FPGA IP
25. Guard Bands Intel® FPGA IP
26. Interlacer Intel® FPGA IP
27. Mixer Intel® FPGA IP
28. Pixels in Parallel Converter Intel® FPGA IP
29. Scaler Intel® FPGA IP
30. Stream Cleaner Intel® FPGA IP
31. Switch Intel® FPGA IP
32. Tone Mapping Operator Intel® FPGA IP
33. Test Pattern Generator Intel® FPGA IP
34. Video Frame Buffer Intel® FPGA IP
35. Video Streaming FIFO Intel® FPGA IP
36. Video Timing Generator Intel® FPGA IP
37. Warp Intel® FPGA IP
38. Design Security
39. Document Revision History for Video and Vision Processing Suite User Guide
22.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N)
22.4.2. Locking to Reference Clock N (from Genlock Controller IP free running)
22.4.3. Setting the VCXO hold over
22.4.4. Restarting the Genlock Controller IP
22.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old)
22.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa)
22.4.7. Disturbing a Reference Clock (a cable pull)
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36.1. About the Video Timing Generator IP
The Video Timing Generator IP provides the real-time signals that define a video raster. The IP can generate any raster, including both interlaced and progressive standards. You configure the IP with a single fixed standard at build time. You can reconfigure dynamically at run-time using the optional processor interface.
Pixels in Parallel Support
The IP can support any number of pixels in parallel from 1 to 8. The IP has no restriction on raster dimensions versus the number of pixels in parallel. The raster width does not have to be an integer multiple of pixels in parallel.
The full-raster output interface contains multiple control words, one per pixel in parallel. The IP can set individual control words, thus allowing any raster width to be correctly output.
The Legacy Clocked Video Output contains multiple F, V, and H, one per pixel in parallel. The IP can set individual F, V, and H, thus allowing any raster width to be correctly output.
The IP can accept timing parameters that are integer multiples of the pixels in parallel, which reduces the gate count of the synthesized IP.
Hard Frame Lock
The hard frame lock allows you to synchronize the output raster to an external timing reference, which you require to genlock the output.
The IP can receive either a timing pulse, or a timing toggle. When the IP detects external timing signal (rising edge only of a pulse, both edges of a toggle) the IP restarts the output raster at your specified pixel location.
The external timing signal might be in a clock domain different to the IP. The period of the external timing signal might contain jitter. The IP places a jitter window, which you specify as a number of clock cycles, around the point when the external timing signal is expected. During this jitter window the IP does not restart the raster.
Diagnostics via processor interface indicate if the raster reset occurs.
Each restart causes a discontinuity in the output timing signals and causes interconnect protocols such as SDI to become invalid for one frame. If the period of the external timing reference and the period of the generated raster do not align, the IP constantly resets and you see no output.
Soft Frame Lock
Soft frame lock allows the output raster to track an external timing reference, but the output clock is not locked to the pixel rate. For example, V-by-One interconnect does not require a pixel-accurate clock.
The IP achieves a soft frame lock by automatically adjusting the total height of the raster at run time.
You specify four regions of the raster where the occurrence of the external timing reference affects the height of the raster:
- Ignore region. A small number of lines before and after the expected timing reference where the total height is not changed.
- Increment region. A small number of lines after the ignore region where the IP increases the total height of the raster by one whole line, if the external timing reference occurs.
- Decrement region. A small number of lines before the ignore region where the IP decreases the total height of the raster by one whole line, if the external timing reference occurs.
- Hard frame lock. The remainder of the raster not included in the ignore, increment, or decrement regions. If the external timing reference occurs in this region, the IP restarts the raster at your specified restart pixel location.
Figure 82. Soft Frame Lock Regions
Variable Refresh Rate
When you turn on variable refresh rate:
- The raster stops at the end of the frame and waits (possibly indefinitely) for the external timing reference. When the IP sees the external timing reference, the IP produces one whole frame, starting with pixel (0,0).
- The IP continues to generate whole lines of raster after the main raster completes. When the IP sees the external timing reference, the current whole line completes, and then the IP produces a pixel (0,0).
- You must turn off both hard frame lock and soft frame lock, because these parameters conflict. The resulting behavior, when the IP detects the external timing reference, is undefined
General-Purpose Pulses and Toggles
The IP can produce up to 8 additional outputs that each provide a pulse or a toggle once per frame.
You can program these general-purpose signals to occur at any fixed point in the raster. Separate parameters specify the first and last pixel of the pulse. If the start and end pixels are the same, the IP generates a single clock pulse. If the end pixel is outside the defined raster, the signal becomes a once-per-frame toggle.