Intel® High Level Synthesis Compiler Standard Edition: User Guide

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ID 683306
Date 12/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Standard Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Simulating Your Design 7. Synthesize your Component with Intel® Quartus® Prime Standard Edition 8. Integrating your IP into a System A. Reviewing the High Level Design Reports (report.html) B. Limitations of the Intel® HLS Compiler Standard Edition C. Intel® HLS Compiler Standard Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
6. Simulating Your Design x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Intel® Quartus® Prime Standard Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High Level Design Reports (report.html) x
A.1. High Level Design Report Layout A.2. Reviewing the Report Summary A.3. Reviewing Loop Information A.4. Reviewing Component Area Usage A.5. Viewing Component Design A.6. Reviewing Your Component Verification Results A.7. Accessing HLD FPGA Reports in JSON Format
A.3. Reviewing Loop Information x
A.3.1. Loop Analysis Example
A.4. Reviewing Component Area Usage x
A.4.1. Area Analysis Example
A.5. Viewing Component Design x
A.5.1. Reviewing Component Interfaces A.5.2. Reviewing Memory Replication and Stallable LSU Information A.5.3. Viewing Your Component Memory System
1. Intel® High Level Synthesis Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Simulating Your Design
7. Synthesize your Component with Intel® Quartus® Prime Standard Edition
8. Integrating your IP into a System
A. Reviewing the High Level Design Reports (report.html)
B. Limitations of the Intel® HLS Compiler Standard Edition
C. Intel® HLS Compiler Standard Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide

A.5.2. Reviewing Memory Replication and Stallable LSU Information

The Component Viewer report in the High Level Design Report (report.html) shows an abstracted netlist of your kernel design. In the Component Viewer, you can visualize load-store units (LSUs) between a component and different memories, streams, and loops.

Consider the following code excerpt from the transpose_and_fold component (part of the tutorial files provided in <QPDS_installdir>/hls/examples/tutorials/loop_memory_dependency): 

01 #include "HLS/hls.h"
02 #include "stdio.h"
03 #include "stdlib.h"
04 
05 #define SIZE 32
06 
07 typedef altera::stream_in<int> my_operand;
08 typedef altera::stream_out<int> my_result;
09 
10 void transpose_and_fold(my_operand &a, my_operand &b, my_result &c)
11 {
12   int i;
13   int j;
14   int a_buf[SIZE][SIZE];
15   int b_buf[SIZE][SIZE];
16   for (i = 0; i < SIZE * SIZE; i++) {
17     a_buf[i / SIZE][i % SIZE] = a.read();
18     b_buf[i / SIZE][i % SIZE] = b.read();
19   }
20 #ifdef USE_IVDEP
21   #pragma ivdep
22 #endif
23   for (j = 0; j < SIZE * SIZE * SIZE; j++) {
24     #pragma unroll
25     for (i = 0; i < SIZE; i++) {
26       b_buf[j % SIZE][i] += a_buf[i][j % SIZE];
27     }
28   }
29   for (i = 0; i < SIZE * SIZE; i++) {
30     c.write(b_buf[i / SIZE][i % SIZE]);
31   }
32 }

The figure below shows that Block3 is highlighted in red to prompt you to review the loop. Because loop analysis of Block3 shows that it is a pipelined loop with an II value of 2, the loop pipeline might affect the throughput of your design. The Component Viewer shows that the II value is caused by a memory dependency on loads to the b_buf variable.

Figure 7. Component View of the transpose_and_fold Component

By hovering your mouse pointer over a node, you can view the tooltip and details that provide more information on the LSU. In the figure below, the tooltip shows information like the latency and that the LSU is stall-free.

Figure 8. Detailed View of Node and Tooltip

The Component Viewer allows you to select the type of connections you want to view. Selecting Control instructs the system viewer to display the connections between blocks and loops. Selecting Memory instructs the function view of the Graph Viewer to display the connections to and from global and local memories. Selecting Streams instructs the system viewer to display the connections reading from and writing to streams.

Figure 9. Component View of the transpose_and_fold Component without Connections between Blocks and Loops
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