Intel® High Level Synthesis Compiler Standard Edition: User Guide

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ID 683306
Date 12/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Standard Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Simulating Your Design 7. Synthesize your Component with Intel® Quartus® Prime Standard Edition 8. Integrating your IP into a System A. Reviewing the High Level Design Reports (report.html) B. Limitations of the Intel® HLS Compiler Standard Edition C. Intel® HLS Compiler Standard Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
6. Simulating Your Design x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Intel® Quartus® Prime Standard Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High Level Design Reports (report.html) x
A.1. High Level Design Report Layout A.2. Reviewing the Report Summary A.3. Reviewing Loop Information A.4. Reviewing Component Area Usage A.5. Viewing Component Design A.6. Reviewing Your Component Verification Results A.7. Accessing HLD FPGA Reports in JSON Format
A.3. Reviewing Loop Information x
A.3.1. Loop Analysis Example
A.4. Reviewing Component Area Usage x
A.4.1. Area Analysis Example
A.5. Viewing Component Design x
A.5.1. Reviewing Component Interfaces A.5.2. Reviewing Memory Replication and Stallable LSU Information A.5.3. Viewing Your Component Memory System
1. Intel® High Level Synthesis Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Simulating Your Design
7. Synthesize your Component with Intel® Quartus® Prime Standard Edition
8. Integrating your IP into a System
A. Reviewing the High Level Design Reports (report.html)
B. Limitations of the Intel® HLS Compiler Standard Edition
C. Intel® HLS Compiler Standard Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide

3. Creating a High-Level Synthesis Component and Testbench

The Intel® HLS Compiler Standard Edition converts individual functions into RTL components. Any function that is not compiled into an RTL component is treated as part of your testbench and is compiled to x86-64 instructions. You can test your components by calling them from your main() function and verifying that the output is correct.

While the compiler supports C++98, you can often achieve better component performance by using the supported subset of C99 whenever possible. The compiler is capable of synthesizing some C++ constructs, which might be easier for you to use to create cleaner code.

For more information about the supported subset of C99 and its restrictions, see "Supported C and C++ Subset for Component Synthesis" in Intel® High Level Synthesis Compiler Standard Edition Reference Manual.

The Intel® HLS Compiler Standard Edition compiles all the code in the function or functions that you label as components, and any code that these components call, to an RTL representation.

You can identify a function in your C++ application that you want to synthesize into an IP core in one of the following ways:

  • Insert the component keyword in the source code before the top-level C++ function to be synthesized.
  • Specify the function on the command line by using the --component <component_list> option of the i++ command.
    To use this option, your component must be configured with C-linkage using the extern "C" specification. For example: 
    extern "C" int myComponent(int a, int b)
Important:

Components are synthesized for all functions labeled with the component keyword and all for all components listed in the --component <component_list> option of the i++ command. Avoid combining these methods because you might unexpectedly synthesize unwanted components.

If you do not want components synthesized for a function, ensure that you do not have the component attribute specified in the function and ensure that the function is not specified in the --component <component_list> option of the i++ command.

You can see which components were synthesized in the Area Analysis by Source section of the high-level design report ( <name>.prj/reports/report.html). For more information about the high-level design report, see The Intel HLS Compiler High-Level Design Reports (report.html).

The HLS compiler creates an executable to run on the CPU. The compiler then sends any calls to functions that you declared as components to simulation of the synthesized IP core, and the simulation results are returned.

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