Intel® High Level Synthesis Compiler Standard Edition: User Guide

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ID 683306
Date 12/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Standard Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Simulating Your Design 7. Synthesize your Component with Intel® Quartus® Prime Standard Edition 8. Integrating your IP into a System A. Reviewing the High Level Design Reports (report.html) B. Limitations of the Intel® HLS Compiler Standard Edition C. Intel® HLS Compiler Standard Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
6. Simulating Your Design x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Intel® Quartus® Prime Standard Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High Level Design Reports (report.html) x
A.1. High Level Design Report Layout A.2. Reviewing the Report Summary A.3. Reviewing Loop Information A.4. Reviewing Component Area Usage A.5. Viewing Component Design A.6. Reviewing Your Component Verification Results A.7. Accessing HLD FPGA Reports in JSON Format
A.3. Reviewing Loop Information x
A.3.1. Loop Analysis Example
A.4. Reviewing Component Area Usage x
A.4.1. Area Analysis Example
A.5. Viewing Component Design x
A.5.1. Reviewing Component Interfaces A.5.2. Reviewing Memory Replication and Stallable LSU Information A.5.3. Viewing Your Component Memory System
1. Intel® High Level Synthesis Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Simulating Your Design
7. Synthesize your Component with Intel® Quartus® Prime Standard Edition
8. Integrating your IP into a System
A. Reviewing the High Level Design Reports (report.html)
B. Limitations of the Intel® HLS Compiler Standard Edition
C. Intel® HLS Compiler Standard Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide

B. Limitations of the Intel® HLS Compiler Standard Edition

When creating your IP using the HLS compiler, be aware of the current set of software and programming limitations.

Compiler support

Linux compiler support

The HLS compiler does not support GCC 4.7.0 or newer. The compiler requires GCC compiler and C++ Libraries version 4.4.7.

Windows compiler support
The HLS compiler for Windows is compatible with Microsoft Visual Studio 2010 only.

C++ Language Restrictions

The Intel® HLS Compiler accepts C++ code.

For the best results when you synthesize your component, code your component function with C99.

  • A component cannot include virtual functions, function pointers, or bit fields.
  • Function-scoped static variables that are a part of the component cannot use function arguments for initialization.
C++ restrictions
  • The HLS compiler does not support certain C++ features such as initializer lists and lambda functions.
Class membership
  • HLS component functions cannot be a C++ class member. However, you can declare your component function as a wrapper function. This wrapper function can call a member function of a class or a part of a namespace.
Exception handling
  • A component cannot contain exception handling.
Library calls
  • The HLS compiler does not currently support calls to C++ runtime libraries on Windows, including calls from the testbench code.
Library functions
  • A component cannot contain standard C or C++ library functions, unless they are explicitly supported by header files provided with the Intel® HLS Compiler.

    A component that contains printf() or cout calls works in its x86 implementation. However, the generated RTL does not include the printf() or cout function calls if you include the HLS/stdio.h library or the HLS/iostream standard C library functions provided with the Intel® HLS Compiler. If you try to generate RTL with the regular stdio.h or iostream headers you will likely experience compiler errors.

Multiple inheritance
  • The HLS compiler does not support classes with multiple inheritance used as parameters. You may use classes as parameters provided that each class inherits from, at most, one class directly.
Namespaces
  • HLS component functions cannot be a part of a declared namespace. However, you can declare your component function as a global wrapper function. This wrapper function can call a member function of a class or a part of a namespace
Overloading/Templates
  • Templated functions or overloaded functions cannot be components. If you need a templated or overloaded function in your component, create a wrapper component and call the templated or overloaded function from the wrapper component.
Parameters
  • The HLS compiler does not support classes with multiple inheritance used as parameters. You may use classes as parameters as long as each class inherits from, at most, one class directly.
Recursion
  • The HLS compiler does not support the synthesis of components that use recursion; however, tail recursion is supported.

    If a component has an algorithm that uses recursion, and it is identified for FPGA acceleration, modify the algorithm to use tail recursion, if possible.

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