Intel® High Level Synthesis Compiler Standard Edition: User Guide

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ID 683306
Date 12/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Standard Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Simulating Your Design 7. Synthesize your Component with Intel® Quartus® Prime Standard Edition 8. Integrating your IP into a System A. Reviewing the High Level Design Reports (report.html) B. Limitations of the Intel® HLS Compiler Standard Edition C. Intel® HLS Compiler Standard Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Standard Edition Compiler-Defined Preprocessor Macros
6. Simulating Your Design x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Intel® Quartus® Prime Standard Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High Level Design Reports (report.html) x
A.1. High Level Design Report Layout A.2. Reviewing the Report Summary A.3. Reviewing Loop Information A.4. Reviewing Component Area Usage A.5. Viewing Component Design A.6. Reviewing Your Component Verification Results A.7. Accessing HLD FPGA Reports in JSON Format
A.3. Reviewing Loop Information x
A.3.1. Loop Analysis Example
A.4. Reviewing Component Area Usage x
A.4.1. Area Analysis Example
A.5. Viewing Component Design x
A.5.1. Reviewing Component Interfaces A.5.2. Reviewing Memory Replication and Stallable LSU Information A.5.3. Viewing Your Component Memory System
1. Intel® High Level Synthesis Compiler Standard Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Simulating Your Design
7. Synthesize your Component with Intel® Quartus® Prime Standard Edition
8. Integrating your IP into a System
A. Reviewing the High Level Design Reports (report.html)
B. Limitations of the Intel® HLS Compiler Standard Edition
C. Intel® HLS Compiler Standard Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Standard Edition User Guide

2. Overview of the Intel® High Level Synthesis (HLS) Compiler Standard Edition

The Intel® High Level Synthesis (HLS) Compiler parses and compiles your your design to an x86-64 object or RTL code optimized for Intel® FPGA device families. It also creates an executable testbench. Use the x86-64 object to quickly test and debug the function of your design.

You can use the same testbench to verify your design both when it is compiled to x86-64 instructions or to HDL.

The Intel® HLS Compiler Standard Edition is command-line compatible with the g++ compiler, and supports most of the g++ compiler flags. See the Intel® High Level Synthesis Compiler Standard Edition Reference Manual for a full list of compiler flags.

The Intel® HLS Compiler recognizes the same file name extensions as g++, namely .c, .C, .cc, .cpp, .CPP, .c++, .cp, and .cxx. The compiler treats all of these file types as C++. The compiler does not explicitly support C, other than as a subset of C++.

Important: The Intel® HLS Compiler Standard Edition treats all input files as C++98. The compiler does not support files conforming to newer C++ standards.
When you target the compilation to an FPGA, the Intel® HLS Compiler outputs an executable and a project directory. The default executable is a.out on Linux and a.exe on Windows. The default project directory is a.prj, and it contains the following outputs:
  • Generated IP
  • High-Level Design Reports (report.html)
  • Verification testbench files
  • Quartus project that you can use to accurately estimate area requirements and fMAX for your design

To specify the name of the compiler output, include the -o <result> option in your i++ command, where <result> is the name of the executable. This command creates a project directory called <result>.prj.

Running the executable file runs your testbench. When you target the compilation to an x86-64 architecture, the output executable runs your design on your CPU like a regular C++ program. The output executable runs very quickly compared to running a simulation of your component RTL. When you target the compilation to an FPGA architecture, the output executable simulates your component RTL. This simulation can take a long time to run.

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