Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 32.  Memory Block Performance Specifications For specification status, see the Data Sheet Status table
Memory Mode Performance Unit
–1V –2V –3V, –3E –4F, –4X
MLAB Single-port RAM/ROM

Simple dual-port RAM

 1,000 782 667 600 MHz
Simple dual-port RAM with read-during-write option 630 510 460 330 MHz
M20K Block40 Single-port RAM/ROM

Simple dual-port RAM

 1,000 (HS)

850 (LP)

 782 (HS)

664 (LP)

 667 (HS)

567 (LP)

 600 (HS)

510 (LP)

 MHz
Simple dual-port RAM, coherent read enabled 1,000 (HS)

850 (LP)

 782 (HS)

664 (LP)

 667 (HS)

567 (LP)

 600 (HS)

510 (LP)

 MHz
Single-port RAM with the read-during-write option set to Old Data

Simple dual-port RAM with the read-during-write option set to Old Data

 800 (HS)

680 (LP)

 640 (HS)

540 (LP)

 560 (HS)

476 (LP)

 480 (HS)

410 (LP)

 MHz
Simple dual-port RAM with ECC enabled, 512 × 32 600 (HS)

500 (LP)

 480 (HS)

400 (LP)

 420 (HS)

357 (LP)

 360 (HS)

300 (LP)

 MHz
Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 1,000 (HS)

850 (LP)

 782 (HS)

664 (LP)

 667 (HS)

567 (LP)

 600 (HS)

510 (LP)

 MHz
Dual-port ROM

True dual-port RAM

 600 (HS) 500 (HS) 420 (HS) 360 (HS) MHz
Simple quad-port RAM 600 (HS) 500 (HS) 420 (HS) 360 (HS) MHz
eSRAM Simple dual-port 750 640 500 500 MHz
Related Information
40 For M20K block, timing/power optimization feature is available. The available options are High Speed (HS) and Low Power (LP). For details on this timing/power optimization feature, refer to the related information.
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