Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

HPS SPI Timing Characteristics

Table 79.  SPI Master Timing Requirements

You can adjust the input delay timing by programming the rx_sample_dly register.

For specification status, see the Data Sheet Status table

Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 — — ns
Tclk SPIM_CLK clock period 16.67 — — ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Tck_jitter SPIM_CLK output jitter — — 2 %
Tdio Master-out slave-in (MOSI) output skew –3 — 2 ns
Tdssfrst 103 SPI_SS_N asserted to first SPIM_CLK edge (1.5 × Tclk) – 2 — — ns
Tdsslst 103 Last SPIM_CLK edge to SPI_SS_N deasserted Tclk  – 2 — — ns
Tsu 104 SPIM_MISO setup time with respect to SPIM_CLK capture edge 5.0 – (rx_sample_dly × Tspi_ref_clk)105 — — ns
Th 104 Input hold in respect to SPIM_CLK capture edge 1.3 + (rx_sample_dly × Tspi_ref_clk) — — ns
Figure 5. SPI Master Output Timing Diagram
Figure 6. SPI Master Input Timing Diagram
Table 80.  SPI Slave Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
Tspi_ref_clk The period of the SPI internal reference clock, sourced from l4_main_clk 2.5 — — ns
Tclk SPIM_CLK clock period 30 — — ns
Tdutycycle SPIM_CLK duty cycle 45 50 55 %
Td Master-in slave-out (MISO) output skew (2 × Tspi_ref_clk) + 3 — (3 × Tspi_ref_clk) + 11 ns
Tsu Master-out slave-in (MOSI) setup time 4 — — ns
Th Master-out slave-in (MOSI) hold time 9 — — ns
Tsuss SPI_SS_N asserted to first SPIM_CLK edge Tspi_ref_clk + 4.2 — — ns
Thss Last SPIM_CLK edge to SPI_SS_N deasserted Tspi_ref_clk + 4.2 — — ns
Figure 7. SPI Slave Output Timing Diagram
Figure 8. SPI Slave Input Timing Diagram
103 SPI_SS_N behavior differs depending on Motorola SPI, TI SSP, or Microwire operational mode.
104 The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising edge.
105 Valid values of rx_sample_dly range from 1 to 64 (units are in Tspi_ref_clk steps).
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