F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

ID 683287
Date 7/06/2024
Public
Document Table of Contents

3.1. Features

You can use the design example to test the following features of the F-Tile Serial Lite IV Intel® FPGA IP:
  • Basic and full transmission modes:
    • Basic mode—This is a pure streaming mode where data is sent without the start-of-packet, empty cycle, and end-of-packet to increase bandwidth. The IP takes the first valid data as the start of a burst.
    • Full mode—This is a packet transfer mode. This mode sends a burst and a sync cycle at the start and end of a packet as delimiters.
  • Transceiver data rate:
    • For PAM4 mode 1 2:
      • FHT supports 48 Gbps to 58 Gbps and 96 Gbps to 116 Gbps per lane with a maximum of 4 lanes.
      • FGT supports 20 Gbps to 58 Gbps per lane with a maximum of 12 lanes.
    • For NRZ mode 1 2:
      • FHT supports 24 Gbps to 29 Gbps and 48 Gbps to 58 Gbps per lane with a maximum of 4 lanes.
      • FGT supports 1 Gbps to 32 Gbps3 per lane with a maximum of 16 lanes.
  • Data error reporting including PCS errors, loss of alignment, CRC errors, and data invalid errors on the RX datapath.
  • Traffic checker for data verification and lane deskew verification.
1 The maximum data rate that the IP can achieve depends on the device speed grade. Refer to the Agilex™ 7 Device Data Sheet for more information about maximum data rate for each device speed grade.
2 Refer to the Parameters section of the F-Tile Serial Lite IV Intel® FPGA IP User Guide for more details on the supported transceiver data rates for PAM4 and NRZ modes.
3 For FGT NRZ mode, 32 Gbps is only supported by the following Agilex™ 7 device OPNs:
  • AGIB027R31B1E2V
  • AGIB027R31B2E2V
  • AGIB027R29A1E2VR3