F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

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ID 683287
Date 7/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for F-Tile Serial Lite IV Design Example 4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives 5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for F-Tile Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. F-Tile Serial Lite IV IP Toolkit 3.8. Analog Parameters 3.9. Deterministic Latency
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.7. F-Tile Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
3.9. Deterministic Latency x
3.9.1. SYSREF Pulse Generator 3.9.2. TX DL Shim Wrapper 3.9.3. RX DL Shim Wrapper 3.9.4. Deterministic Latency Design Considerations
1. About the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for F-Tile Serial Lite IV Design Example
4. F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide Archives
5. Document Revision History for the F-Tile Serial Lite IV Intel® FPGA IP Design Example User Guide

2.3.2. Directory Structure

The Quartus® Prime Pro Edition software generates the design example files in the following folders:
  • <user_defined_design_example_directory>/ed_sim
  • <user_defined_design_example_directory>/ed_synth
  • <user_defined_design_example_directory>/ed_hwtest

The following diagrams show the directories that contain the generated files for the design example.

Figure 5. Directory Structure for Agilex™ 7 F-Tile Serial Lite IV Design Example
Table 5.  Design Example Generated Directory and File Descriptions
Directory/File Description
ed_sim/tb_components The directory that contains the testbench files.
ed_sim/common The directory that contains the .tcl scripts for all the simulators.

ed_sim/cadence

ed_sim/mentor

ed_sim/xcelium

ed_sim/synopsys/vcs

The directories that contain the simulation scripts. These directories also serve as a working area for the simulators.

For simplex Tx/Rx mode:

ed_sim/seriallite4_tx_0

ed_sim/seriallite4_rx_0

For duplex mode:

ed_sim/seriallite4_dup 		The directory that contains the design example simulation source files.

ed_sim/seriallite4_tx_0.ip

ed_sim/seriallite4_rx_0.ip

ed_sim/seriallite4_dup.ip

ed_sim/seriallite4_system_pll.ip

IP-XACT representation of the design.
ed_synth/seriallite_iv_streaming_demo.qpf Quartus® Prime Pro Edition project file.
ed_synth/seriallite_iv_streaming_demo.qsf Quartus® Prime Pro Edition settings file.
ed_synth/seriallite_iv_streaming_demo.sdc Synopsys Design Constraints (SDC) file.
ed_synth/src The directory that contains the design example synthesizable components.
ed_synth/src/seriallite_iv_streaming_demo.v Design example top-level HDL.
ed_synth/demo_control The directory for each synthesizable component including Platform Designer-generated IPs, such as Demo Management and Demo Control modules.
ed_hwtest/sliv_ip_toolkit The directory that contains the .tcl script and package files for the Serial Lite IV IP Toolkit.
ed_hwtest/system_console The directory that contains the system console scripts to provide useful commands for reading statistics and enables you to control various features in the design.
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