Visible to Intel only — GUID: hco1410462422244
Ixiasoft
Visible to Intel only — GUID: hco1410462422244
Ixiasoft
6.6.4. Video Interface
This interface (rxN_video_out) allows access to the video data as a non-Avalon-ST stream. You can use this stream to interface with an external pixel clock recovery function. The stream provides synchronization pulses at the start and end of active lines, and at the start and end of active frames.
The rxN_vid_overflow signal is always valid, regardless of the logical state of rxN_vid_valid. rxN_vid_overflow is asserted for at least one clock cycle when the sink core internal video data FIFO runs into an overflow condition. This condition can occur when the rxN_vid_clk frequency is too low to transport the received video data successfully.
Specify the maximum data color depth in the DisplayPort parameter editor. The same output port transfers both RGB and YCbCr data in 4:4:4, 4:2:2, or 4:2:0 color format. Data is most-significant bit aligned and formatted for 4:4:4.
Color Format | Description |
---|---|
Sub-sampled 4:2:2 color format |
|
Sub-sampled 4:2:0 color format |
|
Pixel Indexes | R Position | G Position | B Position |
---|---|---|---|
0 and 1 |
Y1 |
Y0 |
|
2 and 3 |
Y3 |
Y2 |
|
4 and 5 |
Y5 |
Y4 |
|
... | ... | ... | ... |
If you set Pixel output mode to Dual or Quad, the IP produces two or four pixels in parallel, respectively. To support video resolutions with horizontal active, front and pack porches with lengths that are not divisible by two or four, rxN_vid_valid is widened. For example, for two pixels per clock, rxN_vid_valid[0] is asserted when pixel N belongs to active video and rxN_vid_valid[1] is asserted when pixel n + 1 belongs to active video.
The following figure shows the pixel data order from the least significant bits to the most significant bits.