Visible to Intel only — GUID: vgo1417245086655
Ixiasoft
Visible to Intel only — GUID: vgo1417245086655
Ixiasoft
4.3.1.2. Clock Recovery Interface
The following table lists the signals for the clock recovery core.
Interface |
Port Type |
Clock Domain |
Port |
Direction |
Description |
---|---|---|---|---|---|
control clock |
Clock |
N/A |
clk |
Input |
Control logic clock. This clock runs the loop controller and fPLL reconfiguration related blocks. Intel® recommends you use a 60 MHz clock. |
RX link clock |
Clock |
N/A |
rx_link_clk |
Input |
DisplayPort transceiver link clock. This clock is a divided version of the RX main link clock or divided by 4.
|
reset |
Reset |
clk | areset |
Input |
Asynchronous reset. This is an active-high signal. |
RX link rate |
Conduit |
asynchronous | rx_link_rate[1:0] | Input |
DisplayPort RX link rate.
You need this information for the clock recovery clock to correctly calculate the fPLL parameters. |
RX MSA |
Conduit |
rx_link_clk | rx_msa[216:0] | Input |
A set of different signals containing the following information:
You must connect this set of signals as is from the DisplayPort Intel® FPGA IP to the clock recovery core. |
Video Input |
Conduit |
vidin_clk | vidin_clk | Input |
Pixel clock. |
vidin_data (BPP*PIXELS_PER_CLOCK–1:0) |
Input |
Pixel data. |
|||
vidin_valid | Input |
You must assert this signal when all signals on this port are valid. |
|||
vidin_sol | Input |
Start of video line. |
|||
vidin_eol | Input |
End of video line. |
|||
vidin_sof | Input |
Start of video frame. |
|||
vidin_eof | Input |
End of video frame. |
|||
vidin_locked | Input |
You must assert this signal when the DisplayPort RX is locked to a valid received video stream.
|
|||
Video Output |
Conduit |
rec_clk | rec_clk |
Output |
Reconstructed video clock. |
rec_clk_x2 |
Output |
Reconstructed video clock double frequency. |
|||
vidout (BPP*PIXELS_PER_CLOCK–1:0) |
Output |
Pixel data. |
|||
hsync |
Output |
Horizontal sync. This signal can be active-high or active-low depending on the sync polarity from MSA. |
|||
vsync |
Output |
Vertical sync. This signal can be active-high or active-low depending on the sync polarity from MSA. |
|||
de |
Output |
Data enable. This signal is always active high. |
|||
field2 |
Output |
The clock recovery core asserts this signal during the second video field for interlaced timings. |
|||
reset_out |
Output |
The clock recovery core asserts this signal when the other video output signals are not valid. This signal is asynchronous. |