Visible to Intel only — GUID: hco1410462684509
Ixiasoft
Visible to Intel only — GUID: hco1410462684509
Ixiasoft
11.1.3. DPRX_BER_CONTROL
Address: 0x0002
Direction: CRW
Reset: 0x00000000
Bit |
Bit Name |
Function |
---|---|---|
31:28 |
Unused |
|
27 | RSTI3 | Writing this bit at 1 resets lane 3 bit-error counter in register DPRX_BER_CNTI1. Always reads as ‘0’. |
26 | RSTI2 | Writing this bit at 1 resets lane 2 bit-error counter in register DPRX_BER_CNTI1. Always reads as ‘0’. |
25 | RSTI1 | Writing this bit at 1 resets lane 1 bit-error counter in register DPRX_BER_CNTI0. Always reads as ‘0’. |
24 | RSTI0 | Writing this bit at 1 resets lane 0 bit-error counter in register DPRX_BER_CNTI0. Always reads as ‘0’. |
23 | Unused |
|
22:21 | PHY_SINK_TEST_LANE_SEL | Specifies the lane that is being tested, when PHY_SINK_TEST_LANE_EN is 1,
|
20 | PHY_SINK_TEST_LANE_EN | Writing this bit at 1 enables single lane PHY test, Write 0 to disable single lane PHY test. |
19 |
RST3 | Writing this bit at 1 resets the lane 3 bit-error counter in register DPRX_BER_CNT1. Always reads as 0. |
18 |
RST2 | Writing this bit at 1 resets the lane 2 bit-error counter in register DPRX_BER_CNT1. Always reads as 0. |
17 |
RST1 | Writing this bit at 1 resets lane 1 bit-error counter in register DPRX_BER_CNT0. Always reads as 0. |
16 |
RST0 | Writing this bit at 1 resets lane 0 bit-error counter in register DPRX_BER_CNT0. Always reads as 0. |
15:14 |
Unused |
|
13:11 |
PATT3 | Pattern selection for lane 3:
|
10:8 |
PATT2 | Pattern selection for lane 2:
|
7:5 |
PATT1 | Pattern selection for lane 1:
|
4:2 |
PATT0 | Pattern selection for lane 0:
|
1:0 |
CNTSEL | Count selection:
|