Visible to Intel only — GUID: hco1410462348098
Ixiasoft
Visible to Intel only — GUID: hco1410462348098
Ixiasoft
5.8.5. Transceiver Reconfiguration Interface
You can reconfigure the transceiver to accept a single reference clock. The transceiver reference clocks for the different data rates are shown below:
Devices | Data Rate | Reference Clock Frequency | Description |
---|---|---|---|
Intel FPGA Cyclone 10, Intel FPGA Arria 10 | RBR, HBR, HBR2, HBR3 | 135 MHz | Single reference clock for all HBR* data rates |
Intel FPGA Stratix 10 | RBR, HBR, HBR2, HBR3 | 135 MHz | Reference clock switching required between HBR* rate and UHBR* rate |
UHBR10, UHBR20 | 100 MHz | ||
Intel FPGA Agilex | RBR, HBR, HBR2, HBR3, UHBR10 | 150 MHz | Single reference clock for all HBR* and UHBR* data rates |
*Refer to the respective Design Example User Guides for more details.
During run-time, you can reconfigure the transceiver to operate in either one of the bit rates by changing TX PLL divide ratio.
When the IP makes a request, the tx_reconfig_req port goes high. The user logic asserts tx_reconfig_ack and then reconfigures the transceiver. During reconfiguration, the user logic holds tx_reconfig_busy high. The user logic drives it low when reconfiguration completes.