Visible to Intel only — GUID: hco1410462247396
Ixiasoft
Visible to Intel only — GUID: hco1410462247396
Ixiasoft
2.2. Device Family Support
Device Family | Support Level |
---|---|
Intel® Agilex™ 7 (F-Tile) | Preliminary |
Intel® Stratix® 10 (H-Tile and L-Tile) | Final (for UHBR20, only Preliminary support) |
Intel® Arria® 10 | Final |
Intel® Cyclone® 10 GX | Final |
Arria V GX/GT/GS | Final |
Arria V GZ | Final |
Cyclone V | Final |
Stratix V | Final |
The following terms define device support levels for Intel FPGA IP cores:
- Advance support—the IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
- Preliminary support—the IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
- Final support—the IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
The following table lists the link rate support offered by the DisplayPort Intel® FPGA IP for each Intel FPGA family.
Device Family | Dual Symbol (20-Bit Mode) |
Quad Symbol (40-Bit Mode) |
FPGA Fabric Speed Grade |
---|---|---|---|
Intel® Agilex™ 7 (F-Tile) | RBR, HBR, HBR2 | RBR, HBR, HBR2, HBR3, UHBR10 | 1, 2 |
Intel® Stratix® 10 (H-Tile) | RBR, HBR, HBR2 | RBR, HBR, HBR2, HBR3, UHBR10, UHBR20 (Preliminary support only) | 1, 2, 3 3 |
Intel® Stratix® 10 (L-Tile) | RBR, HBR, HBR2 | RBR, HBR, HBR2, HBR3 | 1, 2, 3 3 |
Intel® Arria® 10 | RBR, HBR, HBR2 | RBR, HBR, HBR2, HBR3 | 1, 2 |
Intel® Cyclone® 10 GX | RBR, HBR, HBR2 | RBR, HBR, HBR2, HBR3 | 5, 6 |
Stratix V | RBR, HBR, HBR2 | RBR, HBR, HBR2 | 1, 2, 3 |
Arria V GX/GT/GS | RBR, HBR | RBR, HBR, HBR2 | 3, 4, 5 |
Arria V GZ | RBR, HBR, HBR2 | RBR, HBR, HBR2 | Any supported speed grade |
Cyclone V | RBR, HBR | RBR, HBR | Any supported speed grade |
Device Family | Adaptive Sync Support |
---|---|
Intel® Agilex™ 7 (F-Tile) | Yes |
Intel® Stratix® 10 (H-Tile and L-Tile) | Yes |
Intel® Arria® 10 | Yes |
Intel® Cyclone® 10 GX | Yes |
To enable the Adaptive Sync feature, refer to Table 30 and Video Interface (TX Video IM Enable = 1). For detailed implementation of the feature, refer to the DisplayPort SST Parallel Loopback with Adaptive Sync Support section in the respective DisplayPort Intel® FPGA IP design example user guides.