Visible to Intel only — GUID: vea1582185376125
Ixiasoft
Visible to Intel only — GUID: vea1582185376125
Ixiasoft
6.3. Sink Non-GPU Mode Support
The DisplayPort sink capability registers are implemented in the IP and support limited features.
DP2.0 Link Rates require GPU mode.
DPCD Offset | DPCD Register | Default Value | Description |
---|---|---|---|
0000h |
DPCD_REV |
12h |
DPCD revision 1.2 |
0001h |
MAX_LINK_RATE |
Configurable through parameter editor |
|
0002h |
MAX_LANE_COUNT |
Configurable through parameter editor |
|
POST_LT_ADJ_REQ_SUPPORTED |
0b |
Not supported | |
TPS3_SUPPORTED |
1b |
Supported | |
ENHANCED_FRAME_CAP |
0b |
Not supported | |
0003h |
MAX_DOWNSPREAD |
1b |
Down-spread up to 0.5% |
NO_AUX_TRANSACTION_LINK_TRAINNG |
1b |
Supported | |
TPS4_SUPPORTED |
1b |
Supported | |
0005h |
DOWN_STREAM_PORT_PRESENT |
00h |
Not supported |
0006h |
MAIN_LINK_CHANNEL_CODING |
01h |
8B/10B |
0007h |
MSA_TIMING_PAR_IGNORED |
0b |
Not supported |
OUI Support |
1b |
Supported | |
000Dh |
eDP CONFIGURATION CAPABILITY |
Configurable through parameter editor |
Indicates that this is an eDP device that can use eDP alternate scrambler reset value of FFFEh |
000Eh |
TRAINING_AUX_RD_INTERVAL |
00h |
|
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT |
1b |
Supported |