Intel® Arria® 10 SoC Development Kit User Guide

Download PDF
ID 683227
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Components 6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide A. Additional Information
1. Intel® Arria® 10 SoC Development Kit Overview x
1.1. General Description 1.2. Board Component Blocks 1.3. Recommended Operating Conditions 1.4. Handling the Board
2. Getting Started x
2.1. Board Inspection 2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software 2.3. Installing the Intel® SoC Embedded Development Suite (EDS) 2.4. Development Kit Installer 2.5. Installing the Intel® FPGA Download Cable Driver 2.6. SD Card Image with Example Software
2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software x
2.2.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe* Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Components x
5.1. Board Overview 5.2. Featured Device: Intel® Arria® 10 SoC 5.3. MAX V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over On-Board Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. On-Board Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughtercards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Additional Information x
A.1. Compliance and Conformity Statements
A.1. Compliance and Conformity Statements x
A.1.1. CE EMI Conformity Caution
1. Intel® Arria® 10 SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Components
6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide
A. Additional Information

5.6.2. JTAG Chain Control DIP Switch

The JTAG chain control DIP switch (SW3) either removes or includes devices in the active JTAG chain.

The SW3 switch select controls the JTAG master/slave select. The DIP switch MSTR switches control the master select. The other 5 pins are bypass pins for the various available JTAG slaves. The following slaves are available and can be bypassed by moving the corresponding bypass switch to the 'ON' position.

Table 22.  JTAG Configuration Modes
Switch 3 Bit Board Label Function
1 Intel® Arria® 10

ON- Intel® Arria® 10 JTAG Bypass

OFF- Intel® Arria® 10 JTAG Enable

2 I/O MAX V

ON- MAXV JTAG Bypass

OFF- MAXV JTAG Enable
3 FMCA

ON- FMCA JTAG Bypass

OFF- FMCA JTAG Enable
4 FMCB

ON- FMCB JTAG Bypass

OFF- FMCB JTAG Enable
5 PCIe

ON- PCIe* JTAG Bypass

OFF- PCIe* JTAG Enable

6 MSTR[0] Refer to Table 23
7 MSTR[1] Refer to Table 23
8 MSTR[2] Refer to Table 23

The MSTR switch settings and their meanings can be seen in the table below.

Table 23.  Modes for Master Switches
MSTR2 MSTR1 MSTR0 Modes
ON ON ON BOOT
OFF ON ON FMCA JTAG Master
ON OFF ON FMCB JTAG Master
ON ON OFF FTRACE JTAG Master
OFF OFF OFF On-Board Intel® FPGA Download Cable II JTAG Master
ON OFF OFF System Configuration Mode
OFF ON OFF GUI Test Mode
OFF OFF ON Reserved

The bypass switch settings dictate which slaves are in/out of the chain, but see below for the order if all were enabled in the chain.

  1. Intel® Arria® 10
  2. IO_MAXV
  3. PCIe*
  4. FMCA
  5. FMCB
Level Two Title