Intel® Arria® 10 SoC Development Kit User Guide

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ID 683227
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Components 6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide A. Additional Information
1. Intel® Arria® 10 SoC Development Kit Overview x
1.1. General Description 1.2. Board Component Blocks 1.3. Recommended Operating Conditions 1.4. Handling the Board
2. Getting Started x
2.1. Board Inspection 2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software 2.3. Installing the Intel® SoC Embedded Development Suite (EDS) 2.4. Development Kit Installer 2.5. Installing the Intel® FPGA Download Cable Driver 2.6. SD Card Image with Example Software
2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software x
2.2.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe* Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Components x
5.1. Board Overview 5.2. Featured Device: Intel® Arria® 10 SoC 5.3. MAX V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over On-Board Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. On-Board Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughtercards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Additional Information x
A.1. Compliance and Conformity Statements
A.1. Compliance and Conformity Statements x
A.1.1. CE EMI Conformity Caution
1. Intel® Arria® 10 SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Components
6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide
A. Additional Information

5.9.11.4. FPGA Debug Port

This debug port needs support of both the HPS 16-bit trace debug port and Blaster direct debug port.

Table 45.  FPGA Debug Port
BANK Pin number Schematic Name

HPS Trace Mode

USER_DIPSW_HPS3 = 0

Blaster Direct Port

USER_DIPSW_HPS3 = 1
2A AM19 FTRACE_D0 HPS 16-bit Trace port D0 Direct_USB_D0
2A AM16 FTRACE_D1 HPS 16-bit Trace port D1 Direct_USB_D1
2A AN16 FTRACE_D2 HPS 16-bit Trace port D2 Direct_USB_D2
2A AP16 FTRACE_D3 HPS 16-bit Trace port D3 Direct_USB_D3
2A AR16 FTRACE_D4 HPS 16-bit Trace port D4 Direct_USB_D4
2A AN19 FTRACE_D5 HPS 16-bit Trace port D5 Direct_USB_D5
2A AP19 FTRACE_D6 HPS 16-bit Trace port D6 Direct_USB_D6
2A AR18 FTRACE_D7 HPS 16-bit Trace port D7 Direct_USB_D7
2A AT18 FTRACE_D8 HPS 16-bit Trace port D8 Direct_USB_RDn
2A AR17 FTRACE_D9 HPS 16-bit Trace port D9 Direct_USB_Wrn
2A AT17 FTRACE_D10 HPS 16-bit Trace port D10 Direct_USB_OEn
2A AT19 FTRACE_D11 HPS 16-bit Trace port D11 Direct_USB_RESETn
2A AU19 FTRACE_D12 HPS 16-bit Trace port D12 Direct_USB_EMPTY
2A AT20 FTRACE_D13 HPS 16-bit Trace port D13 Direct_USB_FULL
2A AU20 FTRACE_D14 HPS 16-bit Trace port D14 Direct_USB_SDA
2A AU17 FTRACE_D15 HPS 16-bit Trace port D15 Direct_USB_SCL
2A AU16 FTRACE_CLK HPS Trace Clock -
2A AP18 USB_FPGA_CLK - Blaster USB Clock
Level Two Title