5.9.12. HPS SPIO Interface
The HPS can monitor and control the following functional signals through the SPI interface:
- HPS LED signals
- HPS Push button and DIP switch signals
- Power good and present signals
- Reset signals
- FMCA/B PCIe* power enable signals
- SFP+ control signals
- I2C master indication signal
- HPS warm reset signals
- PMBUS control signals
| Pin | Description | Function |
|---|---|---|
| nCS | Chip Select | Active low signal that enables the slave device to receive or transfer data from the master device |
| SCK | Serial Clock | The clock signal produced from the master device to synchronize the data transfer |
| MOSI | Serial Data Input | Receive data serially at the positive SCK clock. |
| MISO | Serial Data output | Transmit data serially at the negative SCK clock edge. |
The HPS SPI controller is the SPI master, and the MAX V works as a slave SPI I/O expander. The SPI interface uses 8-bit frame size. For MOSI, the first byte is used as an instruction byte. Bit [7:1] is the register address. Bit [0] is the operation flag where logic '1' is read flag and logic '0' is the write flag. The second byte is the data byte. For MISO, the first byte are zero byte (pad), second byte is the data byte.
Figure 39. HPS SPI Controller Write Timing Diagram
Figure 40. HPS SPI Write Timing (Write/Write)
Figure 41. HPS SPI Read Timing Diagram
Figure 42. HPS SPI Read Timing (Read/Write)
Figure 43. HPS SPI Read Timing (Read/Read)
16 8-bit registers are implemented. For MOSI, the first byte is used as an instruction byte. Bit [7:1] is the register address. Bit [0] is the operation flag: Logic one is read flag. Logic zero is write flag. Second byte is data byte. For MISO, the first byte are zero byte (pad), second byte is data byte.
| Instruction (8bits) | Instruction Description | Register Data Description |
|---|---|---|
| 00000001 | CPLD Revision Value | Register 0: Read-only Register Read value is the CPLD revision value |
| 00000010 | Write HPS LED Registers | Register 1: Bit[7:4] - USER_LED_HPS[3:0], Active low, default value is “0xF” Bit[3:0] - Reserved, default is “0x0” |
| 00000011 | Read HPS LED Registers | Register 1: Bit[7:4] - USER_LED_HPS[3:0] Bit[3:0] - Reserved Default value is “0xF0” |
| 00000101 | Read HPS Push Button and DIP switch registers | Register 2: Current Status of USER_PB_HPS and USER_DIPSW_HPS Bit[7:4] - USER_PB_HPS [3:0] Bit[3:0] - USER_DIPSW_HPS [3:0] |
| 00000110 | Write HPS Push Button IRQ flag clear registers | Register 3: Bit[7] - Write logic one to clear bit 7 flag in register 2, write logic zero to reset this bit after the flag is cleared Bit[6] - Write logic one to clear bit 6 flag in register 2, write logic zero to reset this bit after the flag is cleared Bit[5] - Write logic one to clear bit 5 flag in register 2 , write logic zero to reset this bit after the flag is cleared Bit[4] - Write logic one to clear bit 4 flag in register 2 , write logic zero to reset this bit after the flag is cleared |
| 00000111 | Read HPS Push Button IRQ flag Registers | Register 3: Read-only Register Bit[7:4] - USER_PB_HPS hold registers bits Bit 7: USER_PB_HPS3 IRQ Flag, active low, clear flag by register 3 bit 7. Bit 6: USER_PB_HPS2 IRQ Flag, active low, clear flag by register3 bit 6. Bit 5: USER_PB_HPS1 IRQ Flag, active low, clear flag by register3 bit 5. Bit 4: USER_PB_HPS0 IRQ Flag, active low, clear flag by register3 bit 4. Bit[3:0] - reserved If one of the push buttons is pressed, the corresponding PB’s IRQ register bit is set and A10_SH_GPIO0 is configured to ‘0’. The A10_SH_GPIO0 returns to '1' after the HPS clears the associated bit (even if the PB is still held down). If the second push button is pressed while the HPS is handling the first push button interrupt, the second PB’s IRQ register bit remains as a '0' until HPS clears the interrupt. A10_SH_GPIO0 stays low until the HPS clears the second PB’s IRQ register bit. |
| 00001001 | Read Power good1 Registers | Register 4: Read-only register Bit[7] - operation_flag. ‘1’: Power on finished. ‘0’: The system is in Power down cycle Bit[6] - 1V8_Pgood. ‘1’:1.8V power rail output is normal. ‘0’:1.8V power rail output is abnormal. Bit[5] - 2V5_Pgood. ‘1’:2.5V power rail output is normal. ‘0’:2.5V power rail output is abnormal. Bit[4] - 3V3_Pgood. ‘1’:3.3V power rail output is normal. ‘0’:3.3V power rail output is abnormal. Bit[3] - 5V0_Pgood. ‘1’:5V power rail output is normal. ‘0’:5V power rail output is abnormal. Bit[2] - 0V9_Pgood. ‘1’:0.9V power rail output is normal. ‘0’: 0.9V power rail output is abnormal. Bit[1] - 0V95_Pgood. ‘1’:0.95V power rail output is normal. ‘0’: 0.95V power rail output is abnormal. Bit[0] - 1V0_Pgood. ‘1’:1.0V power rail output is normal. ‘0’: 1.0V power rail output is abnormal. |
| 00001011 | Read Power good2 Registers | Register 5: Read-only register Bit[7] - HPS_Pgood. ‘1’: HPS core power rail output is normal. ‘0’: HPS core power rail output is abnormal. Bit[6] - HILOHPS_VDDPgood. ‘1’:HPS memory power rail output is normal. ‘0’: HPS memory power rail output is abnormal. Bit[5] - HILO_VDDPgood. ‘1’:FPGA memory VDD power rail output is normal. ‘0’: FPGA memory VDD power rail output is abnormal. Bit[4] - HILO_VDDQPgood . ‘1’: FPGA memory VDDQ power rail output is normal. ‘0’: FPGA memory VDDQ power rail output is abnormal. Bit[3] - FMCAVADJPGood. ‘1’:FMCAVADJ power rail output is normal. ‘0’: FMCAVADJ power rail output is abnormal. Bit[2] - FMCBVADJPGood. 1’:FMCBVADJ power rail output is normal. ‘0’: FMCBVADJ power rail output is abnormal. Bit[1] - FAC2MPgood. 1’:FMCA slot powers are normal. ‘0’: FMCA slot powers are abnormal. Bit[0] - FBC2MPgood. 1’:FMCB slot powers are normal. ‘0’: FMCB slot powers are abnormal. |
| 00001101 | Read Power good3 & present Registers | Register 6: Read-only Register Bit[7] - FAM2CPgood. ‘1’:FMCA slot DC power outputs are normal. ‘0’: FMCA slot DC power outputs are abnormal. Bit[6] - 10V_Fail_n. ‘1’: Input voltage is above 10V. ‘0’: Input voltage is below 10V. Bit[5] - BF_PRESENTn. ‘1’: no boot flash card. ‘0’: boot flash present Bit[4] - FILE_PRESENTn. ‘1’: no file flash card. ‘0’: file flash present Bit[3] - FMCA_PRESENTn. ‘1’: no FMCA card. ‘0’: FMCA card present Bit[2] - FMCB_PRESENTn . ‘1’: no FMCB card. ‘0’: FMCB present Bit[1] - PCIE_PRESENTn. ‘1’: no PCIE card. ‘0’: PCIE card present Bit[0] - Reserved |
| 00001110 | Write FMCA/B PCIE Power enable Registers | Register 7 Bit[7] - PCIE_EN. '1': Enable PCIE RC slot power. '0': Disable PCIE RC slot power. Bit[6] - PCIE_AUXEN. '1': Enable PCIE RC slot auxiliary power. '0': Disable PCIE RC auxiliary power. Bit[5:0] - Reserved |
| 00001111 | Read FMCA/B PCIE Power enable Registers | Register 7 Read the status of power enable register. |
| 00010000 | Write HPS Resets Registers | Register 8 Bit[7] - Reserved Bit[6] - Reserved Bit[5] - Reserved Bit[4] - Reserved Bit[3] - Reserved Bit[2] - Reserved Bit[1] - ENET_HPS_RESETn. Active low to reset the HPS Ethernet port Bit[0] - Reserved |
| 00010001 | Read HPS Reset Registers | Register 8 Bit[7] - HPS_UARTA_RESETn. Read-only bit. Always ‘1’ Bit[6] - HPS_WARM_RESETn. Read-only bit. ‘0’: WARM_Reset push button is pressed. ‘1’ No action Bit[5] - HPS_WARM_RESET1n. Read - only bit. ‘0’: Trace reset is detected. ‘1’ No action Bit[4] - HPS_COLD_RESETn. Read-only bit ‘0’: Cold_Reset push button is pressed. ‘1’ No action Bit[3] - HPS_NPOR. Read-only, NPOR for HPS, active low Bit[2] - HPS_NRST. Read-only, NRST for HPS, active low Bit[1] - ENET_HPS_RESETn. Read the status of ENET_HPS_RESETn Bit[0] - ENET_HPS_INTn. ENET_HPS_INTn current status. |
| 00010010 | Write USB & BQSPI& FILE & PCIE Resets Registers | Register 9 Bit[7] - USB_RESET. Active high to reset the HPS USB. Bit[6] - BQSPI_RESETn. Active low to reset the boot flash. Bit[5] - FILE_RESETn. Active low to reset the FILE flash. Bit[4] - PCIE_PERSTn. Active low to reset the PCIE slot. Bit[3:0] - Reserved |
| 00010011 | Read USB & BQSPI& FILE & PCIE Resets Registers | Register 9 Read the status of USB & BQSPI& FILE & PCIE Resets Bit[7] - USB_RESET Bit[6] - BQSPI_RESETn Bit[5] - FILE_RESETn Bit[4] - PCIE_RESETn Bit[3:0] - Reserved |
| 00010100 | Write SFPA Control Registers | Register 10 Bit[7] - SFPA_TXDISABLE. '1': Disable SFPA TX.'0': Enable SFPA TX. Bit[6:5] - SFPA_RATESEL[1:0].SFPA RX rate selection 0: <4.25GBd1: > 4.25GBd Bit[4:0] - Reserved |
| 00010101 | Read SFPA Control Registers | Register 10 Bit[7] - SFPA_TXDISABLE. '1': Disable SFPA TX.'0': Enable SFPA TX. Bit[6:5] - SFPA_RATESEL[1:0].SFPA RX rate selection 0: <4.25GBd1: > 4.25GBd Bit[4] - SFPA_LOS. Loss signal of SFPA. ‘1’:LOS, ‘0’:normal. Bit[3] - SFPA_FAULT. Tx fault signal of SFPA. ‘1’:fault, ‘0’:normal. Bit[2] - SFPA_PRESENTn .Detect signal of SFP module in slot A . ‘1’: no SFP module. ‘0’: SFP module present. Bit[1:0] - Reserved |
| 00010110 | Write SFPB Control Registers | Register 11 Bit[7] - SFPB_TXDISABLE. '1': Disable SFPB TX.'0': Enable SFPB TX. Bit[6:5] - SFPA_RATESEL[1:0].SFPA RX rate selection 0: <4.25GBd1: > 4.25GBd Bit[4:0] - Reserved |
| 00010111 | Read SFPB Control Registers | Register 11 Bit[7] - SFPB_TXDISABLE. Read the status of SFPB TXDISABLE. Bit[6:5] - SFPB_RATESEL[1:0] .Read the status of SFPB rate selection. Bit[4] - SFPB_LOS. Read the Los signal of SFPB.'1': Loss '0': Normal. Bit[3] - SFPB_FAULT. Read the Tx Fault signal of SFPB.'1': Fault '0': Normal. Bit[2] - SFPB_PRESENTn.Detect signal of SFP module in slot B. ‘1’: no SFP module. ‘0’: SFP module present Bit[1:0] - Reserved |
| 00011001 | Read I2C master Register | Register 12 Bit[7] - I2C master indication. ‘1’ :HPS is the I2C master,’0’ MAXV is the I2C master Bit[6:0] - Reserved |
| 00011010 | Write HPS Warm reset Register | Register 13 Bit[7:6] - “00” Bit[5] - HPS_SPI_WARM_RESETn. Active low to warm reset HPS; MAX V automatically clears this bit 1us after it becomes active. Bit[4:0] - “00000” |
| 00011011 | Read HPS Warm reset Register | Register 13 Bit[7:6] - “00” Bit[5] - HPS_SPI_WARM_RESETn. Read the status of HPS SPI warm reset. Bit[4:0] - “00000” |
| 00011100 | Write HPS Warm Reset Key Register | Register 14 Bit[7:0] - key register of HPS warm reset. Value of 0xA8 allows bit5 in register13 to be recognized. Software must write a different value to this register after a valid write to bit5 in Register13. |
| 00011101 | Read HPS Warm Reset Key Register | Register 14 Value currently in HPS Warm Reset Key register. |
| 00011110 | Write PM Bus Control Register | Register 15 Bit[7] - A10PMBUSEN. '1': Enable the Intel® Arria® 10 FPGA PMBUS. '0': Disable the Intel® Arria® 10 FPGA PMBUS. Bit[6] - A10_PMBUSDIS_N. '1': Enable the System MAX5/HPS PMBus.'0': Disable the System MAX5/HPS PMBus. Bit[5:0] - Reserved |
| 00011111 | Read PM Bus Control Register | Register 15 Bit[7] - A10PMBUSEN. '1': The Intel® Arria® 10 FPGA PMBUS is enabled. '0: The Intel® Arria® 10 FPGA PMBUS is disabled. Bit[6] - A10_PMBUSDIS_N. '1': The System MAXV/HPS PMBus is enabled.'0': The System MAXV/HPS PMBus is disabled. Bit[5] - Pmbus_Altertn. '1': I2C is normal.'0' : I2C Hangs Bit[4:0] - Reserved |