Intel® Arria® 10 SoC Development Kit User Guide

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ID 683227
Date 2/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 SoC Development Kit Overview 2. Getting Started 3. Development Board Setup 4. Board Test System 5. Board Components 6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide A. Additional Information
1. Intel® Arria® 10 SoC Development Kit Overview x
1.1. General Description 1.2. Board Component Blocks 1.3. Recommended Operating Conditions 1.4. Handling the Board
2. Getting Started x
2.1. Board Inspection 2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software 2.3. Installing the Intel® SoC Embedded Development Suite (EDS) 2.4. Development Kit Installer 2.5. Installing the Intel® FPGA Download Cable Driver 2.6. SD Card Image with Example Software
2.2. Installing the Subscription Edition of the Intel® Quartus® Prime Design Software x
2.2.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Board 3.2. Default Switch and Jumper Settings
4. Board Test System x
4.1. Preparing the Board 4.2. Running the Board Test System 4.3. Version Selector 4.4. Using the Board Test System
4.4. Using the Board Test System x
4.4.1. Using the Configure Menu 4.4.2. The System Info Tab 4.4.3. The GPIO Tab 4.4.4. The XCVR Tab 4.4.5. The PCIe* Tab 4.4.6. The FMCA Tab 4.4.7. The FMCB Tab 4.4.8. The DDR3 Tab 4.4.9. The DDR4 Tab 4.4.10. The EEPROM Tab 4.4.11. The Power Monitor 4.4.12. The Clock Control
5. Board Components x
5.1. Board Overview 5.2. Featured Device: Intel® Arria® 10 SoC 5.3. MAX V CPLD 5M2210 System Controller 5.4. Configuration 5.5. Status Elements 5.6. Setup Elements 5.7. General User Input/Output 5.8. Clock Circuitry 5.9. Components and Interfaces 5.10. Memory 5.11. Board Power Supply
5.4. Configuration x
5.4.1. System Controller Configuration 5.4.2. FPGA and I/O MUX CPLD Programming over On-Board Intel® FPGA Download Cable II 5.4.3. FPGA Programming by HPS 5.4.4. FPGA Programming by EPCQ Device 5.4.5. FPGA Programming over External Intel® FPGA Download Cable
5.6. Setup Elements x
5.6.1. Board Settings DIP Switch 5.6.2. JTAG Chain Control DIP Switch 5.6.3. Reference Clock Source Selection 5.6.4. CPU Reset Push Button 5.6.5. Logic Reset Push Button
5.7. General User Input/Output x
5.7.1. Character LCD
5.8. Clock Circuitry x
5.8.1. On-Board Oscillators
5.9. Components and Interfaces x
5.9.1. PCIe 5.9.2. 10/100/1000 Ethernet (HPS) 5.9.3. 10/100/1000 Ethernet (FPGA) 5.9.4. FMC 5.9.5. HPS Shared I/O 5.9.6. USB 2.0 Port (HPS) 5.9.7. RS-232 UART (HPS) 5.9.8. Real-Time Clock (HPS) 5.9.9. SFP+ 5.9.10. I2C Interface 5.9.11. FPGA General I/O Configuration 5.9.12. HPS SPIO Interface
5.9.11. FPGA General I/O Configuration x
5.9.11.1. FPGA-I/O MAX V Interface 5.9.11.2. LMK04828 Controller 5.9.11.3. FPGA Resistor MUX 5.9.11.4. FPGA Debug Port 5.9.11.5. FPGA PMBUS VID 5.9.11.6. FPGA Auxiliary Signals
5.10. Memory x
5.10.1. FPGA External Memory 5.10.2. HPS External Memory 5.10.3. HPS Boot Flash Interface 5.10.4. I2C EEPROM 5.10.5. Daughtercards
5.11. Board Power Supply x
5.11.1. Power Distribution System 5.11.2. Power Measurement
A. Additional Information x
A.1. Compliance and Conformity Statements
A.1. Compliance and Conformity Statements x
A.1.1. CE EMI Conformity Caution
1. Intel® Arria® 10 SoC Development Kit Overview
2. Getting Started
3. Development Board Setup
4. Board Test System
5. Board Components
6. Document Revision History for the Intel® Arria® 10 SoC Development Kit User Guide
A. Additional Information

3.2. Default Switch and Jumper Settings

This topic shows you how to restore the default factory settings and explains their functions.
CAUTION:
Do not install or remove jumpers (shunts) while the development board is powered on.
Figure 4. Default Switch and Jumper Settings
Note: The Switch position is represented by the black box.

To restore the switches to their factory default settings, perform these steps:

  1. Set the DIP switch bank (SW1) to match the SW1 DIP Switch Settings table and the Default Switch and Jumper Settings figure.
    Note: In the following table, ON indicates the switch is to the upper position according to the board orientation as shown in the Default Switch and Jumper Settings figure.
    Table 4.  SW1 Factory Default Settings
    Switch Bit Name Bit Function Default Position
    1 I2C flag Switch 1.1 has the following options:
    • ON (0) = System MAX V is the I2C master
    • OFF (1) = HPS is the I2C master
    		OFF
    2 DC_POWER_CTRL Switch 1.2 has the following options:
    • ON (0) = Power off PCIe* slot when it is present
    • OFF (1) = Power up PCIe* directly
    		OFF
    3 factory_load Switch 1.3 has the following options:
    • ON (0) = Load user design from flash at power up
    • OFF (1) = Load factory design from flash at power up
    		 OFF
    4 security_mode Reserved OFF
    Table 5.  SW4 Switch Settings
    Switch Bit Name Bit Function Default Position
    1 Reserved Reserved OFF
    2 MSEL0 Switch 4.2 has the following options:
    • ON (Up) = MSEL0 is 1
    • OFF (Down) = MSEL0 is 0
    		 OFF
    3 MSEL1 Switch 4.3 has the following options:
    • ON (Up) = MSEL1 is 1
    • OFF (Down) = MSEL1 is 0
    		OFF
    4 MSEL2 Switch 4.4 has the following options:
    • ON (Up) = MSEL2 is 1
    • OFF (Down) = MSEL2 is 0
    		OFF
    Table 6.  MSEL Settings for each Configuration Scheme of Intel® Arria® 10 SoC Devices
    Configuration Vccpgm (V) Power-On Reset (POR delay) Valid MSEL [2:0]
    JTAG-based configuration - - Use any valid MSEL pin settings below
    AS-Active Serial (x1 and x4) 1.8 Fast 010
        Standard 011
    PS-Passive Serial 1.2/1.5/1.8 Fast 000
        Standard 001

  2. Set the DIP switch bank (SW3) to match the following tables:
    Table 7.  SW3 Factory Default Settings
    Switch Board Label Function Default Position
    1 Intel® Arria® 10

    ON- Intel® Arria® 10 JTAG Bypass

    OFF- Intel® Arria® 10 JTAG Enable

    		OFF
    2 IO MAX® V

    ON- MAX V JTAG Bypass

    OFF- MAX V JTAG Enable     		OFF
    3 FMCA

    ON- FMCA JTAG Bypass

    OFF- FMCA JTAG Enable

    		 ON
    4 FMCB

    ON- FMCB JTAG Bypass

    OFF- FMCB JTAG Enable

    		 ON
    5 PCIe*

    ON- PCIe* JTAG Bypass

    OFF- PCIe* JTAG Enable

    		ON
    6 MSTR0 On-Board Intel® FPGA Download Cable II JTAG Master OFF
    7 MSTR1 On-Board Intel® FPGA Download Cable II JTAG Master OFF
    8 MSTR2 On-Board Intel® FPGA Download Cable II JTAG Master OFF

  3. Set the following jumper blocks to match the table below:
    Table 8.  Default Jumper Settings
    Board Reference Board Label Description Default Position
    J16, J17 OSC2_CLK_SEL
    • 00 (SHORT, SHORT): Selects the on-board 25MHz clock
    • 01 (SHORT, OPEN): Selects SMA clock which connected to J15
    • 10 (OPEN, SHORT): Selects the on-board 33MHz clock
    • 11 (OPEN, OPEN): none
    		 SHORT, SHORT
    J30 HPS Core Voltage
    • SHORT: HPS core 0.95 V
    • OPEN: HPS core 0.9 V
    		 SHORT
    J32 Voltage of FMCBVADJ
    • No SHORT: 1.1 V
    • SHORT 1 and 2: 1.2 V
    • SHORT 3 and 4: 1.25 V
    • SHORT 5 and 6: 1.35 V
    • SHORT 7 and 8: 1.5 V
    • SHORT 9 and 10: 1.8 V
    		 SHORT 9 and 10
    J42 Voltage of FMCAVADJ
    • No SHORT: 1.1 V
    • SHORT 1 and 2: 1.1 V
    • SHORT 3 and 4: 1.2 V
    • SHORT 5 and 6: 1.35 V
    • SHORT 7 and 8: 1.5 V
    • SHORT 9 and 10: 1.8 V
    		 SHORT 9 and 10
    Table 9.   Default Jumper BSEL Settings for Micro-SD Daughtercard
    Board Reference Description Default BSEL Value = 0x4 Default Position
    J3 BSEL0 0 SHORT left 2 pins
    J4 BSEL1 0 SHORT upper 2 pins1
    J5 BSEL2 1 SHORT upper 2 pins1
Related Information
1 The directions of these pins are in reference to the board arrangement as in the Default Switch and Jumper Settings figure.
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