External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 11/03/2022
Public

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6.5.6.5. Power Delivery Recommendations for DDR4 Discrete Configurations

This topic describes power distribution network (PDN) design guidelines for the memory side in discrete topologies.
Note: For information on power distribution network design at the FPGA to meet timing margins, refer to the Intel® Agilex™ PDN design guidelines.

In the following table, the number of decoupling capacitors is based on a single channel. If multiple channels are sharing the same power rail, the number of decoupling capacitors at the memories must be scaled accordingly for all channels.

Physically small decoupling capacitors are recommended to minimize area, inductance, and resistance on the PDN path on the printed circuit board.

Table 117.  Required Decoupling Capacitors on the PCB for the Memory Side
Memory Configuration Power Domain Decoupling Location Quantity × Value (size)
Discrete (Component) Single Rank x8 VDDQ/VDD shorted 4 near each x8 DRAM device 36 x 1uF (0402)
Distribute around DRAM devices 9 x 10uF (0603)
VPP 2 near each x8 DRAM device 18 x 1uF (0402)
Distribute around DRAM devices 5 x 10uF (0603)
VTT Place near Rtt (termination resistors) 16 x 1uF (0402)
Place near Rtt (termination resistors) 4 x 10uF (0603)
Discrete (Component) Single Rank x16 VDDQ/VDD shorted 4 near each x16 DRAM device 18 x 1uF (0402)
Distribute around DRAM devices 5 x 10uF (0603)
VPP 2 near each x16 DRAM device 10 x 1uF (0402)
Distribute around DRAM devices 3 x 10uF (0603)
VTT Place near Rtt (termination resistors) 8 x 1uF (0402)
Place near Rtt (termination resistors) 2 x 10uF (0603)