External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 11/03/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1.14. emif_usr_clk for DDR4

User clock interface
Table 27.  Interface: emif_usr_clkInterface type: Clock Output
Port Name Direction Description
emif_usr_clk Output User clock domain