External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 11/03/2022
Public

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11.7.2.3. Enabling the EMIF Toolkit in an Existing Design

To enable toolkit support in an existing design, follow these steps.
  1. Add the following line to the qsf file: set_global_assignment -name VERILOG_MACRO "ALTERA_EMIF_ENABLE_ISSP=1"
  2. For each instance of EMIF in the design, set Intel Quartus Prime EMIF Debug Toolkit/On-Chip Debug Port > Add EMIF Debug Interface.
  3. In the Calibration IP, ensure that the value for Quartus Prime EMIF Debug Toolkit/On-Chip Debug Portis set to Add EMIF Debug Interface.
  4. Generate HDL and compile your design.
Note: If your design was not generated based on the design example, you must regenerate the design beginning with a design example. Refer to the instructions in Generating a Design Example with the Debug Toolkit.