Visible to Intel only — GUID: yma1510156869236
Ixiasoft
Visible to Intel only — GUID: yma1510156869236
Ixiasoft
4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
Display Name | Description |
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Simulation | Specifies that the system generate all necessary file sets for simulation when you click Generate Example Design. Expect an additional 1-2 minute delay when generating the simulation fileset. If you do not enable this parameter, the system does not generate simulation file sets. Instead, the output directory contains the ed_sim.qsys file which contains details of the simulation example design for Platform Designer, and a make_sim_design.tcl file with other corresponding tcl files. You can run the make_sim_design.tcl file from a command line to generate a simulation example design. The generated example designs for various simulators reside in the /sim subdirectory. |
Synthesis | Specifies that the system generate all necessary file sets for synthesis when you click Generate Example Design. Expect an additional 1-2 minute delay when generating the synthesis file set. If you do not enable this parameter, the system does not generate synthesis file sets. Instead, the output directory contains the ed_synth.qsys file which contains details of the synthesis example design for Platform Designer, and a make_qii_design.tcl file with other corresponding tcl files. You can run the make_qii_design.tcl file from a command line to generate a synthesis example design. The generated example design resides in the /qii subdirectory. |
Display Name | Description |
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Simulation HDL format | Format of HDL files generated for simulating the design example. |