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1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface FPGA IP User Guide
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.6. Register Map IP-XACT Support for HBM2 IP
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design
5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa*
5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS*
5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO*
5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator
5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency
5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals
6.3. User AXI Interface Timing
6.4. User APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller
6.6. Soft AXI Switch
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth
7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency
7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency
7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing
7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
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6.5.3. Controller Idle State Status
User logic can read the HBM2 controller idle status values from APB address 16'h000E.
Read Data Bit Definition | Description |
---|---|
[0] | Read Command Queue Idle for PC0. |
[1] | Read Command Queue Idle for PC1. |
[2] | Write Command Queue Idle for PC0. |
[3] | Write Command Queue Idle for PC1. |
[4] | PC0 Timer Idle. |
[5] | PC1 Timer Idle. |
[7:6] | Reserved. |
[8] | PC0 AXI Read Data Idle. |
[9] | PC1 AXI Read Data Idle. |
[10] | PC0 AXI Write Data Idle. |
[11] | PC1 AXI Write Data Idle. |
[15:12] | Reserved. |