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1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface FPGA IP User Guide
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.6. Register Map IP-XACT Support for HBM2 IP
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design
5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa*
5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS*
5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO*
5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator
5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency
5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals
6.3. User AXI Interface Timing
6.4. User APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller
6.6. Soft AXI Switch
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth
7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency
7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency
7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing
7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
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6.5. User-controlled Accesses to the HBM2 Controller
You can use the APB interface in applications when you need to directly control the HBM2 Refresh commands and access HBM2 Controller Status registers.
For information on using the APB interface signals, refer to User APB Interface Timing.
Each physical HBM2 channel is mapped to its own sideband register space. The APB address accesses are byte-address based. If a write is issued to an unaligned address, it is ignored (that is, read returns 0 and write has no effect.) The sideband register map is shared between the two HBM2 Pseudo Channels and the allocation of addresses is organized as follows:
- Registers common to both Pseudo-Channels:
- Address map – 16’h0000-16’h00FF.
- Includes Refresh (per-bank, all banks), Self-Refresh, Temperature Readout and Power down status.
Note: The register bit descriptions of Pseudo Channel 0 (PC0) and Pseudo Channel 1 (PC1) in the registers common to both Pseudo Channels apply to the bottom HBM2 interface. For the top HBM2 interface, the PC0 and PC1 register bit definitions are swapped. - Register Map for individual Pseudo Channels:
- Address map – Pseudo Channel 0 (16’h0100- 16’h01FF) and Pseudo Channel 1 (0x200-0x2FF).
- This map is used to access ECC and Interrupt Status Registers for each Pseudo Channel.
Note: The register address maps for individual Pseudo Channel 0 (PC0) and Pseudo Channel 1 (PC1) as shown above apply to the bottom HBM2 interface. For the top HBM2 interface, the PC0 and PC1 register address maps are swapped.