Visible to Intel only — GUID: gvn1523123100198
Ixiasoft
Visible to Intel only — GUID: gvn1523123100198
Ixiasoft
6.5.5. ECC Error Status
ECC registers provide the following information – and corresponding APB addresses – for Pseudo Channel 0 and Pseudo Channel 1:
- Single-bit error (SBE) counter
- Double-bit error (DBE) counter
- Logical address (AXI address) of the first single-bit error
- Logical address (AXI address) of the first double-bit error
- Read transaction ID (AXI) of the first single-bit error
- Read transaction ID (AXI) of the first double-bit error
- Read Data Parity error counter
The values of the ECC registers are read when the PRREADY output from the HBM2 controller is asserted. When the HBM2 controller is RESET, these register values are reset to zero.
Address | Read Data Bit Location | Description |
---|---|---|
16’h0120 – PC0 16’h0220 – PC1 |
[7:0] | Single-Bit-Error Counter. The counter does not overflow when value reaches maximum. Write 0 to clear the counter. Clearing the counter does not clear this valid bit or vice-versa. You must issue a separate write command to valid and counter to clear both registers. |
[15:8] | Reserved. | |
16’h0122 – PC0 16’h0222 – PC1 |
[7:0] | Double-Bit-Error Counter. The counter does not overflow when value reaches maximum. Write 0 to clear the counter. Clearing the counter does not clear this valid bit or vice-versa. You must issue a separate write command to valid and counter to clear both registers. |
[15:8] | Reserved. | |
16’h0124 – PC0 16’h0224 – PC1 |
[15:0] | First SBE logical address (lower order). This is the logical address of the first single-bit error, corresponding to the lower 16 bits of the AXI Address bus. |
16’h0126 – PC0 16’h0226 – PC1 |
[15:0] | First SBE logical address (higher order). This is the logical address of the first single-bit error, corresponding to the higher 16 bits of the AXI address bus. The higher order 4 bits in 4GB configuration and higher-order 3 bits in 8GB configuration are padded with zeros. |
16’h0128 – PC0 16’h0228 - PC1 |
[15:0] | First DBE logical address (lower order). This is the logical address of the first double-bit error, corresponding to the lower 16 bits of the AXI address bus. |
16’h012A – PC0 16’h022A – PC1 |
[15:0] | First DBE logical address (higher order). This is the logical address of the first double-bit error, corresponding to the higher 16 bits of the AXI address bus. The higher order 4 bits in 4GB configuration and higher order 3 bits in 8GB configuration are padded with zeros. |
16’h012C – PC0 16’h022C – PC1 |
[8:0] | Read Transaction ID of the first single-bit error. |
[15:9] | Reserved. | |
16’h012E – PC0 16’h022E – PC1 |
[8:0] | Read Transaction ID of the first double-bit error. |
[15:9] | Reserved. | |
16’h0130 – PC0 16’h0230 – PC1 |
[7:0] | Read Data Parity Error Count. The counter does not overflow when value reaches maximum. Write 0 to clear the counter. Clearing the counter does not clear this valid bit or vice-versa. You must issue a separate write command to valid and counter to clear both registers. |
[15:8] | Reserved. |