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1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface FPGA IP User Guide
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.6. Register Map IP-XACT Support for HBM2 IP
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design
5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa*
5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS*
5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO*
5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator
5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency
5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals
6.3. User AXI Interface Timing
6.4. User APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller
6.6. Soft AXI Switch
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth
7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency
7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency
7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing
7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
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6.2.7. Sideband APB Interface
The sideband APB interface allows user logic to issue refresh commands and also provides access to the controller status signals. Each HBM2 channel has one APB Interface.
Port Name | Width | Direction | Description |
---|---|---|---|
ur_paddr | 16 | Input | APB address bus. You can use the APB address bus to access the MMR register space, to issue specific user-requested commands. |
ur_psel | 1 | Input | Select. The user interface generates this signal to indicate that the channel APB interface is selected and that a data transfer is required. There is a PSEL signal for each HBM2 channel APB interface and this signal can be tied HIGH. |
ur_penable | 1 | Input | Enable. This signal indicates the start of an APB transfer. |
ur_pwrite | 1 | Input | Write/Read access. When this signal is HIGH, it indicates an APB write access. When this signal is LOW, it indicates an APB read access. |
ur_pwdata | 16 | Input | Write data. This signal is driven by user logic during write cycles when PWRITE is HIGH. |
ur_pstrb | 2 | Input | Write strobes (byte enables). This signal indicates which byte lanes to update during a write transfer. There is one write strobe for each eight bits of the write data bus. Write transfers to the HBM2 controller require both the byte enables to be active and hence must be driven to 2’b11. Write strobes must not be active during a read transfer. |
ur_prready | 1 | Output | Ready. This signal indicates the completion of a write or read transaction. |
ur_prdata | 16 | Output | Read data. The read data bus provides useful HBM2 controller information and status signals. |