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1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface FPGA IP User Guide
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.6. Register Map IP-XACT Support for HBM2 IP
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design
5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa*
5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS*
5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO*
5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator
5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency
5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals
6.3. User AXI Interface Timing
6.4. User APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller
6.6. Soft AXI Switch
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth
7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency
7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency
7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing
7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
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6.2.8. Avalon® Memory-Mapped (AVMM) Interface Signals
The following AVMM interface signals are provided per HBM2 Pseudo Channel.
Port Name | Direction | Width | Description |
---|---|---|---|
ctrl_amm_0_0_waitrequest_n | Output | 1 | Asserts when HBM is busy. |
ctrl_amm_0_0_read | Input | 1 | Read request. |
ctrl_amm_0_0_write | Input | 1 | Write request. |
ctrl_amm_0_0_address | Input | 28/29 | Write or read address, 28-bits wide for 4G device, 29-bits wide for 8-G device. |
ctrl_amm_0_0_readdata | Output | 256 | Read data. |
ctrl_amm_0_0_writedata | Input | 256 | Write data. |
ctrl_amm_0_0_burstcount | Input | 7 | AVMM burst count, set to 7’h1 for BL4, 7’h2 for burst length 8. |
ctrl_amm_0_0_byteenable | Input | 32 | Byte-enable for write data. |
ctrl_amm_0_0_readdatavalid | Output | 1 | Asserts when read data is valid. |
ctrl_ecc_readdataerror_0_0 | Output | 1 | Asserts high by the controller ECC logic to indicate that the read data has an uncorrectable error. |
ctrl_auto_precharge_0_0 | Input | 1 | Available when the Enable Auto Precharge Control option is selected in Controller Configuration. When asserted high along with a read or write request to the memory controller, indicates that auto-precharge is enabled. |
ctrl_user_priority_0_0 | Input | 1 | Available when the Enable Command Priority Control option is selected in Controller Configuration. When asserted high along with a read or write request to the memory controller, indicates that the request is high priority and should be fulfilled before other low priority requests. |
For information on using the Avalon® memory-mapped interface, refer to Avalon Interface Specifications.
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