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1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface FPGA IP User Guide
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.6. Register Map IP-XACT Support for HBM2 IP
Simulation Assumptions
Supported Simulators
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design
5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa*
5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS*
5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO*
5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator
5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency
5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals
6.3. User AXI Interface Timing
6.4. User APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller
6.6. Soft AXI Switch
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth
7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency
7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency
7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing
7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
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5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
This section describes how to simulate the generated HBM2 IP.
Simulation Assumptions
The parameter settings that you make on the Controller tab affect efficiency during simulation. In the default configuration, with the default parameter settings, the traffic generator issues sequential transactions.
Supported Simulators
The HMB2 IP supports the following simulators:
- ModelSim SE
- Questa* Advanced Simulator
- Questa*-Intel FPGA Edition
- Aldec Riviera-PRO*
- Synopsys* VCS
- Xcelium* Parallel Simulator
Section Content
High Bandwidth Memory (HBM2) Interface Intel FPGA IP Example Design
Simulating High Bandwidth Memory (HBM2) Interface Intel FPGA IP with ModelSim* and Questa*
Simulating High Bandwidth Memory (HBM2) Interface Intel FPGA IP with Synopsys VCS*
Simulating High Bandwidth Memory (HBM2) Interface Intel FPGA IP with Riviera-PRO*
Simulating High Bandwidth Memory (HBM2) Interface Intel FPGA IP with Cadence Xcelium* Parallel Simulator
Simulating High Bandwidth Memory (HBM2) Interface Intel FPGA IP for High Efficiency
Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project