High Bandwidth Memory (HBM2) Interface FPGA IP User Guide

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ID 683189
Date 3/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 2. Introduction to High Bandwidth Memory 3. Stratix® 10 HBM2 Architecture 4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface 7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance 8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives 9. Document Revision History for High Bandwidth Memory (HBM2) Interface FPGA IP User Guide
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
1.1. Release Information
2. Introduction to High Bandwidth Memory x
2.1. HBM2 in Intel® Stratix® 10 Devices 2.2. HBM2 DRAM Structure 2.3. Stratix® 10 HBM2 Features 2.4. Stratix® 10 HBM2 Controller Features
3. Stratix® 10 HBM2 Architecture x
3.1. Stratix® 10 HBM2 Introduction 3.2. Stratix® 10 UIB Architecture 3.3. Stratix® 10 HBM2 Controller Architecture
3.3. Stratix® 10 HBM2 Controller Architecture x
3.3.1. Stratix® 10 HBM2 Controller Details
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
4.1. Creating an Quartus® Prime Pro Edition Project for High Bandwidth Memory (HBM2) Interface FPGA IP 4.2. Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.3. Pin Planning for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2. Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP 4.2.6. Register Map IP-XACT Support for HBM2 IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP x
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design 5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa* 5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS* 5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO* 5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator 5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency 5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface x
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram 6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals 6.3. User AXI Interface Timing 6.4. User APB Interface Timing 6.5. User-controlled Accesses to the HBM2 Controller 6.6. Soft AXI Switch
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals x
6.2.1. Clock Signals 6.2.2. Reset Signals 6.2.3. Calibration Status Signals 6.2.4. Memory Interface Signals 6.2.5. User-interface Signals 6.2.6. AXI User-interface Signals 6.2.7. Sideband APB Interface 6.2.8. Avalon® Memory-Mapped (AVMM) Interface Signals
6.3. User AXI Interface Timing x
6.3.1. AXI Write Transaction 6.3.2. AXI Read Transaction 6.3.3. Improving User Logic to HBM2 Controller AXI Interface Timing
6.4. User APB Interface Timing x
6.4.1. Advanced Peripheral Bus Protocol 6.4.2. APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller x
6.5.1. User-controlled Refreshes 6.5.2. Temperature and Calibration Status Readout 6.5.3. Controller Idle State Status 6.5.4. Power Down Status 6.5.5. ECC Error Status 6.5.6. User Interrupt 6.5.7. ECC Error Correction and Detection
6.5.6. User Interrupt x
6.5.6.1. Interrupt Enable and Conditions for Interrupt Generation 6.5.6.2. Interrupt Status 6.5.6.3. Error Valid Status
6.6. Soft AXI Switch x
6.6.1. AXI Switch Selection in HBM2 IP Catalog GUI
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance x
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth 7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency 7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency 7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing 7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface FPGA IP User Guide

5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design

The following illustration shows a high-level block diagram of the HBM2 example design that provides the simulation environment for the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP when generated for simulation.
Figure 12. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Generated for Simulation

The Traffic Generator emulates a real-world application that writes to, and reads back from memory and validates the read data. You can modify the traffic generator logic to fit your traffic pattern or drive the transactions to the HBM2 memory with your own logic.

Simulation incorporates an abstract model of the hardened HBM2 controller and the universal interface block (UIB). The HBM2 controller performs data reordering and enhancement functions, and allows communication between the AXI4 user interface and the UIB PHY. The universal interface block PHY (UIB PHY) is the physical-layer interface that carries low-level signaling.

The HBM2 Model is an abstract generic model representative of the HBM2 DRAM for simulation. This is not a vendor-specific model.

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