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1. About the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
2. Introduction to High Bandwidth Memory
3. Stratix® 10 HBM2 Architecture
4. Creating and Parameterizing the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
5. Simulating the High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
6. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Interface
7. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Performance
8. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide Archives
9. Document Revision History for High Bandwidth Memory (HBM2) Interface FPGA IP User Guide
4.2.1. General Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.2. FPGA I/O Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.3. Controller Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.4. Diagnostic Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.5. Example Designs Parameters for High Bandwidth Memory (HBM2) Interface Intel® FPGA IP
4.2.6. Register Map IP-XACT Support for HBM2 IP
5.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Example Design
5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa*
5.3. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Synopsys VCS*
5.4. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Riviera-PRO*
5.5. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with Cadence Xcelium* Parallel Simulator
5.6. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP for High Efficiency
5.7. Simulating High Bandwidth Memory (HBM2) Interface IP Instantiated in Your Project
6.1. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP High Level Block Diagram
6.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Controller Interface Signals
6.3. User AXI Interface Timing
6.4. User APB Interface Timing
6.5. User-controlled Accesses to the HBM2 Controller
6.6. Soft AXI Switch
7.1. High Bandwidth Memory (HBM2) DRAM Bandwidth
7.2. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP HBM2 IP Efficiency
7.3. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Latency
7.4. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP Timing
7.5. High Bandwidth Memory (HBM2) Interface Intel® FPGA IP DRAM Temperature Readout
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5.2. Simulating High Bandwidth Memory (HBM2) Interface Intel® FPGA IP with ModelSim* and Questa*
- Launch the ModelSim simulator.
- Select File > Change Directoryand navigate to: project_directory/sim/ed_sim/sim/mentor
- Verify that the Transcript window is visible; if it is not, display it by selecting View > Transcript.
- In the Transcript window, run source msim_setup.tcl at the bottom of the ModelSim tool screen.
- After the Tcl script finishes running, run ld_debug in the Transcript window. This command compiles the design files and elaborates the top-level design.
- After ld_debug finishes running, the Objects window appears. In the Objects window, select the signals to simulate by right-clicking and selecting Add Wave from the context menu.
For example, if you want to see the HBM2 interface signals, select the module mem0_0 from the Instance window. With mem0_0 selected, go to the Objects window and select the signals that you want to see. (If the Objects window is not visible, you can display it by selecting View > Objects.
- To run the HBM2 simulation, type run -all.
If the simulation is not visible, select View > Wave. With the Wave window open, select File > Save Format. Click OK to capture your selected waveforms in a wave.do file. To display the waveforms, type do wave.do, and then type run -all.Whenever you make changes to the design or to the wave.do, you must repeat step 7 of this procedure. Alternatively, you can combine the instructions into a script and run that script instead. The following example illustrates a run.do script containing the necessary commands:
if {[file exists msim_setup.tcl]} { source msim_setup.tcl ld_debug do wave.do run -all } else { error "The msim_setup.tcl script does not exist. Please generate the example design RTL and simulation scripts. See ../../README.txt for help." }
Save the run.do script in the same directory as the msim_setup.tcl file. Type do run.do to run this script from the Transcript window. - Upon completion of the simulation, the Transcript window displays efficiency data and other useful information.