Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide

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ID 683187
Date 3/12/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS) 2. Installing the Tools 3. Running the Tools 4. SoC EDS Licensing 5. Arm* Development Studio* for Intel® SoC FPGA Edition 6. Boot Tools User Guide 7. Hardware Library 8. Using the HPS Flash Programmer 9. Bare Metal Compilers 10. SD Card Boot Utility 11. Linux* Device Tree Generator 12. Support and Feedback
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS) x
1.1. Notice 1.2. Tool Versions 1.3. Differences Between Standard and Professional Editions 1.4. Overview 1.5. Hardware and Software Development Roles 1.6. Hardware – Software Development Flow 1.7. Introduction to the Intel® SoC FPGA EDS Revision History
1.5. Hardware and Software Development Roles x
1.5.1. Hardware Engineer 1.5.2. Bare Metal and RTOS Developer 1.5.3. Linux* Kernel and Driver Developer 1.5.4. Linux* Application Developer
2. Installing the Tools x
2.1. Installation Folders 2.2. Linux 2.3. Windows 2.4. Installing the Intel® SoC FPGA EDS Document Revision History
2.2. Linux x
2.2.1. Installing SoC EDS 2.2.2. Installing Arm* DS* 2.2.3. Installing Linaro* Bare Metal Toolchain
2.3. Windows x
2.3.1. Installing SoC EDS 2.3.2. Installing Arm* DS* 2.3.3. Installing Cygwin 2.3.4. Installing MinGW 2.3.5. Installing Linaro* Bare Metal Toolchain
3. Running the Tools x
3.1. Linux* 3.2. Windows* 3.3. Running the Tools Revision History
4. SoC EDS Licensing x
4.1. Getting the License 4.2. Activating the License 4.3. Intel® SoC FPGA EDS Licensing Revision History
5. Arm* Development Studio* for Intel® SoC FPGA Edition x
5.1. Arm* DS* for Intel® SoC FPGA Edition Revision History
6. Boot Tools User Guide x
6.1. Introduction 6.2. BSP Generator 6.3. Bootloader Image Tool (mkpimage) 6.4. U-Boot Image Tool (mkimage) 6.5. Building the Bootloader 6.6. Boot Tools User Guide Revision History
6.2. BSP Generator x
6.2.1. BSP Generation Flow 6.2.2. BSP Generator Graphical User Interface 6.2.3. BSP Generator Command Line Interface 6.2.4. BSP Files and Folders 6.2.5. BSP Settings
6.2.1. BSP Generation Flow x
6.2.1.1. Cyclone® V SoC and Arria® V SoC Flow 6.2.1.2. Intel® Arria® 10 SoC Flow
6.2.3. BSP Generator Command Line Interface x
6.2.3.1. bsp-create-settings
6.3. Bootloader Image Tool (mkpimage) x
6.3.1. Operation 6.3.2. Header File Format 6.3.3. Tool Usage 6.3.4. Output Image Layout
6.3.4. Output Image Layout x
6.3.4.1. Base Address 6.3.4.2. Size 6.3.4.3. Address Alignment 6.3.4.4. Padding
6.3.4.3. Address Alignment x
6.3.4.3.1. NAND Flash 6.3.4.3.2. Serial NOR Flash 6.3.4.3.3. SD/MMC
6.4. U-Boot Image Tool (mkimage) x
6.4.1. Tool Options 6.4.2. Usage Examples
6.5. Building the Bootloader x
6.5.1. Building the Cyclone® V SoC and Arria® V SoC Preloader 6.5.2. Building the Intel® Arria® 10 SoC Bootloader 6.5.3. Building the Intel® Stratix® 10 SoC and Intel® Agilex™ Devices
7. Hardware Library x
7.1. Feature Description 7.2. Hardware Library Reference Documentation 7.3. System Memory Map 7.4. Hardware Library Revision History
7.1. Feature Description x
7.1.1. SoC Abstraction Layer (SoCAL) 7.1.2. HW Manager
8. Using the HPS Flash Programmer x
8.1. HPS Flash Programmer Command-Line Utility 8.2. How the HPS Flash Programmer Works 8.3. Using the Flash Programmer from the Command Line 8.4. Supported Memory Devices 8.5. HPS Flash Programmer User Guide Revision History
8.3. Using the Flash Programmer from the Command Line x
8.3.1. HPS Flash Programmer 8.3.2. HPS Flash Programmer Command Line Examples
9. Bare Metal Compilers x
9.1. Arm* Bare Metal Compilers 9.2. Linaro* GCC Compiler 9.3. Bare Metal Compilers Revision History
10. SD Card Boot Utility x
10.1. Usage Scenarios 10.2. Tool Options 10.3. SD Card Boot Utility Revision History
11. Linux* Device Tree Generator x
11.1. Linux* Device Tree Generator Revision History
12. Support and Feedback x
12.1. Support and Feedback Revision History
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS)
2. Installing the Tools
3. Running the Tools
4. SoC EDS Licensing
5. Arm* Development Studio* for Intel® SoC FPGA Edition
6. Boot Tools User Guide
7. Hardware Library
8. Using the HPS Flash Programmer
9. Bare Metal Compilers
10. SD Card Boot Utility
11. Linux* Device Tree Generator
12. Support and Feedback

8.4. Supported Memory Devices

Table 7.  QSPI Flash
Flash Device Manufacturer Device ID DIE # Density (Mb) Voltage
M25P40 Micron 0x132020 1 4 3.3
N25Q064 Micron 0x17BA20 1 64 3.3
N25Q128 Micron 0x18BA20 1 128 3.3
N25Q128 Micron 0x18BB20 1 128 1.8
N25Q256 Micron 0x19BA20 1 256 3.3
N25Q256 Micron 0x19BB20 1 256 1.8
MT25QL512 Micron 0x20BA20 1 512 3.3
N25Q512 Micron 0x20BA20 2 512 3.3
MT25QU512 Micron 0x20BB20 1 512 1.8
N25Q512A Micron 0x20BB20 2 512 1.8
N25Q00AA Micron 0x21BA20 4 1024 3.3
MT25QU01G Micron 0x21BB20 2 1024 1.8
N25Q00AA Micron 0x21BB20 4 1024 1.8
MT25QL02G Micron 0x22BA20 4 2048 3.3
MT25QU02G Micron 0x22BB20 4 2048 1.8
S25FL128S Cypress 0x182001 1 128 (64KB Sectors) 3.3
S25FL128S Cypress 0x182001 1 128 (256KB Sectors) 3.3
S25FL256S Cypress 0x190201 1 256 (64KB Sectors) 3.3
S25FL256S Cypress 0x190201 1 256 (256KB Sectors) 3.3
S25FL512S Cypress 0x200201 1 512 3.3
MX25L12835E Macronix 0x1820C2 1 128 3.3
MX25L25635 Macronix 0x1920C2 1 256 3.3
MX66L51235F Macronix 0x1A20C2 1 512 3.3
MX66L1G45 Macronix 0x1B20C2 1 1024 3.3
MX66U51235 Macronix 0x3A25C2 1 512 1.8
GD25Q127C GigaDevice 0x1840C8 1 128 3.3
Table 8.  ONFI Compliant NAND Flash
Manufacturer MFC ID Device ID Density (Gb)

Micron

0x2C

0x68

32

Micron

0x2C

0x48

16

Micron

0x2C

0xA1

8

Micron

0x2C

0xF1

8

Note: The above table contains just examples of supported devices. The HPS Flash Programmer supports all ONFI compliant NAND flash devices that are supported by the HPS QSPI Flash Controller.
Note: The HPS Flash Programmer supports Intel® Arria® 10 SoC devices. For more information, refer to the "Supported Flash Devices for Intel® Arria® 10 SoC" web page.
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