Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide

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ID 683187
Date 3/12/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS) 2. Installing the Tools 3. Running the Tools 4. SoC EDS Licensing 5. Arm* Development Studio* for Intel® SoC FPGA Edition 6. Boot Tools User Guide 7. Hardware Library 8. Using the HPS Flash Programmer 9. Bare Metal Compilers 10. SD Card Boot Utility 11. Linux* Device Tree Generator 12. Support and Feedback
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS) x
1.1. Notice 1.2. Tool Versions 1.3. Differences Between Standard and Professional Editions 1.4. Overview 1.5. Hardware and Software Development Roles 1.6. Hardware – Software Development Flow 1.7. Introduction to the Intel® SoC FPGA EDS Revision History
1.5. Hardware and Software Development Roles x
1.5.1. Hardware Engineer 1.5.2. Bare Metal and RTOS Developer 1.5.3. Linux* Kernel and Driver Developer 1.5.4. Linux* Application Developer
2. Installing the Tools x
2.1. Installation Folders 2.2. Linux 2.3. Windows 2.4. Installing the Intel® SoC FPGA EDS Document Revision History
2.2. Linux x
2.2.1. Installing SoC EDS 2.2.2. Installing Arm* DS* 2.2.3. Installing Linaro* Bare Metal Toolchain
2.3. Windows x
2.3.1. Installing SoC EDS 2.3.2. Installing Arm* DS* 2.3.3. Installing Cygwin 2.3.4. Installing MinGW 2.3.5. Installing Linaro* Bare Metal Toolchain
3. Running the Tools x
3.1. Linux* 3.2. Windows* 3.3. Running the Tools Revision History
4. SoC EDS Licensing x
4.1. Getting the License 4.2. Activating the License 4.3. Intel® SoC FPGA EDS Licensing Revision History
5. Arm* Development Studio* for Intel® SoC FPGA Edition x
5.1. Arm* DS* for Intel® SoC FPGA Edition Revision History
6. Boot Tools User Guide x
6.1. Introduction 6.2. BSP Generator 6.3. Bootloader Image Tool (mkpimage) 6.4. U-Boot Image Tool (mkimage) 6.5. Building the Bootloader 6.6. Boot Tools User Guide Revision History
6.2. BSP Generator x
6.2.1. BSP Generation Flow 6.2.2. BSP Generator Graphical User Interface 6.2.3. BSP Generator Command Line Interface 6.2.4. BSP Files and Folders 6.2.5. BSP Settings
6.2.1. BSP Generation Flow x
6.2.1.1. Cyclone® V SoC and Arria® V SoC Flow 6.2.1.2. Intel® Arria® 10 SoC Flow
6.2.3. BSP Generator Command Line Interface x
6.2.3.1. bsp-create-settings
6.3. Bootloader Image Tool (mkpimage) x
6.3.1. Operation 6.3.2. Header File Format 6.3.3. Tool Usage 6.3.4. Output Image Layout
6.3.4. Output Image Layout x
6.3.4.1. Base Address 6.3.4.2. Size 6.3.4.3. Address Alignment 6.3.4.4. Padding
6.3.4.3. Address Alignment x
6.3.4.3.1. NAND Flash 6.3.4.3.2. Serial NOR Flash 6.3.4.3.3. SD/MMC
6.4. U-Boot Image Tool (mkimage) x
6.4.1. Tool Options 6.4.2. Usage Examples
6.5. Building the Bootloader x
6.5.1. Building the Cyclone® V SoC and Arria® V SoC Preloader 6.5.2. Building the Intel® Arria® 10 SoC Bootloader 6.5.3. Building the Intel® Stratix® 10 SoC and Intel® Agilex™ Devices
7. Hardware Library x
7.1. Feature Description 7.2. Hardware Library Reference Documentation 7.3. System Memory Map 7.4. Hardware Library Revision History
7.1. Feature Description x
7.1.1. SoC Abstraction Layer (SoCAL) 7.1.2. HW Manager
8. Using the HPS Flash Programmer x
8.1. HPS Flash Programmer Command-Line Utility 8.2. How the HPS Flash Programmer Works 8.3. Using the Flash Programmer from the Command Line 8.4. Supported Memory Devices 8.5. HPS Flash Programmer User Guide Revision History
8.3. Using the Flash Programmer from the Command Line x
8.3.1. HPS Flash Programmer 8.3.2. HPS Flash Programmer Command Line Examples
9. Bare Metal Compilers x
9.1. Arm* Bare Metal Compilers 9.2. Linaro* GCC Compiler 9.3. Bare Metal Compilers Revision History
10. SD Card Boot Utility x
10.1. Usage Scenarios 10.2. Tool Options 10.3. SD Card Boot Utility Revision History
11. Linux* Device Tree Generator x
11.1. Linux* Device Tree Generator Revision History
12. Support and Feedback x
12.1. Support and Feedback Revision History
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS)
2. Installing the Tools
3. Running the Tools
4. SoC EDS Licensing
5. Arm* Development Studio* for Intel® SoC FPGA Edition
6. Boot Tools User Guide
7. Hardware Library
8. Using the HPS Flash Programmer
9. Bare Metal Compilers
10. SD Card Boot Utility
11. Linux* Device Tree Generator
12. Support and Feedback

8.3.1. HPS Flash Programmer

The HPS flash programmer utility can erase, blank-check, program, verify, and examine the flash. The utility accepts a Binary File with a required ".bin" extension.

The HPS flash programmer command-line syntax is: 

quartus_hps <options> <file.bin>
Note: The HPS flash programmer uses byte addressing.
Table 6.  HPS Flash Programmer Parameters
Option Short Option Required Description
--addr -a

Yes (if the start address is not 0)

This option specifies the start address of the operation to be performed.

--cable -c

Yes

This option specifies what download cable to use.

To obtain the list of programming cables, run the command "jtagconfig". It lists the available cables, like in the following example:
jtagconfig
  • Intel® FPGA Download Cable [USB-0]
  • Intel® FPGA Download Cable [USB-1]
  • Intel® FPGA Download Cable [USB-2]
The "-c" parameter can be the number of the programming cable, or its name. The following are valid examples for the above case:
  • -c 1
  • -c " Intel® FPGA Download Cable [USB-2]"
--device -d

Yes (if there are multiple HPS devices in the chain)

This option specifies the index of the HPS device. The tool automatically detects the chain and determine the position of the HPS device; however, if there are multiple HPS devices in the chain, the targeted device index must be specified.

--boot N/A Yes

Option to reconfigure the HPS IOCSR and PINMUX before starting flash programming.

For the Intel® Quartus® Prime HPS Flash Programmer options:
  • Warm/cold reset HPS (BootROM) so that BootROM can reconfigure the setting.

    FPGA (for Intel® Arria® 10 SoC) is nconfig.

  • Explicitly configure dedicated I/O and PINMUX
Available options:
  • 1 - Set Breakpoint to halt CPU, warm reset HPS [not recommended]2
  • 2 - Set Watchpoint to halt CPU, warm reset HPS3
  • 3 - Explicitly configure dedicated IO and PINMUX4
  • 16 - Cold reset HPS5

Cyclone® V SoC and Intel® Arria® 10 SoC support values: 1, 2 and 16.

Intel® Arria® 10 SoC supports values: 2, 3 and 16
Note: For the first three options, add up integer of 16, so that the HPS cold reset is performed
Available options for a cold reset before the flow:
  • 17 - Cold reset HPS + breakpoint6
  • 18 - Cold reset HPS + watchpoint7
  • 19 - Cold reset HPS + configure dedicated IO and PINMUX8
--exit_xip N/A Yes (if the QSPI flash device has been put into XIP mode) This option exits the QSPI flash device from XIP mode. A non-zero value has to be specified for the argument. For example, quartus_hps -c <cable> -o <operation> --exit_xip=0x80.
--operation -o

Yes

This option specifies the operation to be performed. The following operations are supported:

  • I—Read IDCODE of SOC device and discover Access Port
  • S—Read Silicon ID of the flash
  • E—Erase flash
  • B—Blank-check flash
  • P—Program flash
  • V—Verify flash
  • EB—Erase and blank-check flash
  • BP—Program <BlankCheck> flash
  • PV—Program and verify flash
  • BPV—Program (blank-check) and verify flash
  • X—Examine flash
Note: The program begins with erasing the flash operation before programming the flash by default.
--size -s

No

This option specifies the number of bytes of data to be performed by the operation. size is optional.

Note: The following options: repeat and interval must be used together and are optional.

The HPS BOOT flow supports up to four images where each image is identical. These options duplicate the operation data; therefore you do not need embedded software to create a large file containing duplicate images.

--repeat -t No repeat—specifies the number of duplicate images for the operation to perform.
--interval -i No interval—specifies the repeated address. The default value is 64 kilobytes (KB).
2 Warm reset HPS for BootROM to configure dedicated IO and PINMUX, and use a breakpoint to halt CPU.
3 Warm reset HPS for BootROM to configure dedicated IO and PINMUX, and use a watchpoint to halt CPU.
4 Explicitly configure dedicated IO and PINMUX.
5 Bit-wise on top of the flow, if you set the bit, the tool will perform cold reset first
6 Cold reset HPS for BootROM to configure dedicated IO and PINMUX, and use a breakpoint to halt CPU.
7 Cold reset HPS for BootROM to configure dedicated IO and PINMUX, and use a watchpoint to halt CPU.
8 Cold reset HPS, then explicitly configure dedicated IO and PINMUX.
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