AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

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ID 683183
Date 12/18/2017
Public
Document Table of Contents
Document Table of Contents x
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report x
Hardware Requirements Hardware Setup AD9371 EVM Software Setup Hardware Checkout Methodology for JESD204B Transmitter JESD204B IP Core and DAC Configurations Hardware Checkout Methodology for JESD204B Receiver JESD204B IP Core and Main ADC Configurations Deterministic Latency (Subclass 1) Test Results Test Result Comments Document Revision History for AN 792: Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
Hardware Checkout Methodology for JESD204B Transmitter x
Transmitter Data Link Layer Transmitter Transport Layer Scrambling
Transmitter Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Hardware Checkout Methodology for JESD204B Receiver x
Receiver Data Link Layer Receiver Transport Layer Descrambling
Receiver Data Link Layer x
Code Group Synchronization (CGS) Initial Frame and Lane Synchronization
Intel FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report

Test Result Comments

In each test case, both the JESD204B transmitter and JESD204B receiver IP core successfully initialize from CGS phase, ILAS phase, and until user data phase.

The test results for JESD204B transmitter are marked with Pass with comments because the deframer of AD9371 raises IRQ due to ILAS configuration mismatch. The conflicting ILAS parameters are N value and CS value. The AD9371 deframer register contains the following JESD204B parameter values N=14 and CS=2 while FPGA transmits ILAS with following JESD204B parameter N=16 and CS=0. The FPGA is configured with JESD204B parameters as per values defined in AD9371-User-Guide-UG-992 document available at the time of testing (refer Figure 15). Otherwise the behavior of the JESD204B transmitter IP core meets the passing criteria.

Figure 15. Snapshot of datasheet describing JESD204B parameters of DAC datapath.

The monotone sine wave from FPGA is transmitted into RF domain successfully at desired frequency and when loopbacked into ADC, the original monotone sine wave is received back.

In the deterministic latency measurement, consistent total latency is observed across the JESD204B transmitter link and JESD204B receiver link.

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